DMA, The Hidden Key to DSP Systems

Mr. Steven D. Krueger

Wireless Infrastructure Group
Texas Instruments
Dallas, TX

Friday, April 12th, 3:00 PM, ENS 637

Abstract

The key to inexpensive but high-performance computation is having the right data in high speed memory when its needed. The largely predictable access patterns of signal processing algorithms make it possible to accurately predict which data will be needed and when. The trick then is getting the right data from peripheral or high-latency memory into memory accessible with low latency by the processor. Virtually every DSP chip contains DMA (direct memory access) function that works largely autonomously to move data from peripherals or high-latency memory into high bandwidth, low latency memory near the processor.

The DMA controller is also used to avoid processor interrupts that rob processor of cycles for productive computation. DMA controllers serve this function well by handling many I/O events that would have generated an interrupt to the processor in less sophisticated systems.

DMA controllers can serve both purposes effectively and at low cost. We'll review the conditions that makes this an optimal system organization for signal processing systems and explore the capabilities of advanced DMA functions.

Biography

Mr. Steven D. (Steve) Krueger received his S.M. in Computer Science, and S.B. in Electrical Engineering from Massachusetts Institute of Technology in 1980. Mr. Krueger is a Distinguished Member of Technical Staff in TI's C6000 DSP Architecture Roadmap organization where has responsibilities for instruction set architecture definition, compatibility and extension. He maintains the detailed instruction set specifications used internally by both IC designers and compiler writers.

Mr. Krueger has previously worked on system and instruction set architecture for several TI and other microprocessors. He recently collaborated with ARM Ltd. on the requirements and definition of the ARM v6 architecture. While in TI's SPARC processor product group, Mr. Krueger served as TI's representative to SPARC International's SPARC Architecture Committee and participated in the development of SPARC version 9, the 64-bit extended SPARC architecture. During this time he was also active in the IEEE 1754 standards effort to specify a standard processor architecture.

In the 1980's, Mr. Krueger was in TI's Computer Science Laboratory where his research interests were computer architecture and hardware/software interfaces. He was responsible for the architecture of the Explorer Lisp Machine processor and its successors.

Mr. Krueger joined Texas Instruments in 1980 and has been with the company for over twenty years.

A list of Telecommunications and Signal Processing Seminars is available at from the ECE department Web pages under "Seminars". The Web address for the Telecommunications and Signal Processing Seminars is http://signal.ece.utexas.edu/seminars