Merged Arithmetic for Digital Signal Processing

Abstract

Multiplication and addition are fundamental arithmetic operations utilized in digital signal processing systems. Many options have been examined for the design of discrete VLSI adders and discrete VLSI multipliers. However, better solutions are available if the multiplications and additions are merged into a single design which performs both operations. The design of high-speed word-parallel multipliers facilitates the incorporation of additional operations. This research examines the merging of fixed point multiplication and addition into one design. The merged implementation of multiply-add, multi-term multiply summation, and add-multiply is examined in terms of area, timing, and power requirements. The performance of these merged designs is examined in the implementation of lattice filters and symmetric FIR filters.

While previous merged arithmetic designs offer reduced latency or reduced area over designs implemented with discrete multipliers and adders, these designs had some characteristics not well suited for VLSI implementation. This research extends merged arithmetic by supporting different arrival times of the input operands, introducing a partially merged arithmetic that enhances scalability in the number of multiplication and addition terms, and representation in two's complement notation. This research also introduces analysis of pipelining these merged arithmetic designs and their power consumption characteristics.

Biography

A list of Telecommunications and Signal Processing Seminars is available at from the ECE department Web pages under "Seminars". The Web address for the Telecommunications and Signal Processing Seminars is http://signal.ece.utexas.edu/seminars