Streaming SIMD Extension

• 70 new instructions

• 8 new 128-bit SSE registers (OS support)

• Execute two SSE instructions simultaneously

  • Double-cycle through existing 64-bit hardware
  • 2 micro-ops per SSE instruction
  • Latency often two cycles or greater

• Explicit scalar SSE instructions

• Prefetch to various levels of cache

• Non-allocating stores

• 10% increase in die area

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