>>>> DSK3A C3x DSP Starter Kit Assembler Rev 1.17 >>>> (c) Copyright 1994-1995 Texas Instruments Incorporated >>>> Mon Oct 27 14:45:18 1997 >>>> SCAN.ASM >>>> >>>> Include Open : C3XMMRS.ASM >>>> Include Close: C3XMMRS.ASM >>>> >>>> PASS 1 Complete >>>> Errors: 0 Warnings: 0 >>>> 0x00809802 nocode ;**************************************************************** 0x00809802 nocode ; SCAN.ASM for TMS320C31 DSP STARTERS KIT 0x00809802 nocode ; Keith Larson 0x00809802 nocode ; TMS320 DSP Applications 0x00809802 nocode ; (C) Copyright 1995,1996 0x00809802 nocode ; Texas Instruments Incorporated 0x00809802 nocode ; 0x00809802 nocode ; This is unsupported freeware with no implied warranties or 0x00809802 nocode ; liabilities. See the disclaimer document for details 0x00809802 nocode ; 0x00809802 nocode ; NOTE: A shareware 640x480x256 BGI SVGA graphics driver was 0x00809802 nocode ; used to develop this application. It is NOT distributed 0x00809802 nocode ; the DSK software. You must obtain this driver from the 0x00809802 nocode ; original author. Read README. for details. 0x00809802 nocode ;----------------------------------------------------------------; 0x00809802 nocode ; This code is designed to drive the TSL1402 256 x1 Linear Sensor; 0x00809802 nocode ; Array using the following circuit for the C3x DSK. The best ; 0x00809802 nocode ; construction technique is as shown. Normaly the components ; 0x00809802 nocode ; would be placed on the ground plane side of the project board ; 0x00809802 nocode ; but in this case the light needs to hit the device from the ; 0x00809802 nocode ; bottom. ; 0x00809802 nocode ; ; 0x00809802 nocode ; The project boards I prefer to use have a solid ground plane ; 0x00809802 nocode ; on one side (component side) and pads on the other. This type ; 0x00809802 nocode ; of board has proven to be very reliable and easy to use with ; 0x00809802 nocode ; excellent analog signals. ; 0x00809802 nocode ; ; 0x00809802 nocode ; In my case mounting of the TSL1402 was achieved by removing ; 0x00809802 nocode ; a small piece of the ground plane. This was done cutting the ; 0x00809802 nocode ; plane (not very deep) and then by soldering a piece of ; 0x00809802 nocode ; solder-wick to the plane so it could be pulled away. This ; 0x00809802 nocode ; will slightly damage the underlying fiberglass, but is not too ; 0x00809802 nocode ; drastic. ; 0x00809802 nocode ; ; 0x00809802 nocode ; If you use a board with a ground plane and choose to leave the ; 0x00809802 nocode ; ground plane intact, use a wire-wrap socket with leads that are; 0x00809802 nocode ; long enough to easily solder or wire-wrap to without causing a ; 0x00809802 nocode ; short to the ground plane. ; 0x00809802 nocode ; ; 0x00809802 nocode ; NOTE: The TLC5510 8 bit flash converter is an ideal converter ; 0x00809802 nocode ; for this application. However since this device is only ; 0x00809802 nocode ; available in surface mount and is not as easy to wire ; 0x00809802 nocode ; up it is not showcased with this application note. ; 0x00809802 nocode ;----------------------------------------------------------------; 0x00809802 nocode ; ; 0x00809802 nocode ; DSK (side view) ; 0x00809802 nocode ; ; 0x00809802 nocode ; +---+ ; 0x00809802 nocode ; +-------+ | C | ; 0x00809802 nocode ;DB25 | +----+| | A | +------+ ; 0x00809802 nocode ; | |PWR || | P | |RCA | ; 0x00809802 nocode ; +-| || | | | +-+ ; 0x00809802 nocode ; ============================================= ; 0x00809802 nocode ; | | | | <- Female conns ; 0x00809802 nocode ; +------------+ +------------+ go here ; 0x00809802 nocode ; ; 0x00809802 nocode ; ; 0x00809802 nocode ;(component side) ; 0x00809802 nocode ; |||||||||||| |||||||||||| <- Male conns ; 0x00809802 nocode ;Gnd plane side|||||||||||| |||||||||||| go here ; 0x00809802 nocode ; ============================================= ; 0x00809802 nocode ;Pad side | | ; 0x00809802 nocode ; ===== ; 0x00809802 nocode ; | | TLS1402 ; 0x00809802 nocode ; +---+ ; 0x00809802 nocode ; ^ ; 0x00809802 nocode ; | ; 0x00809802 nocode ; Focused ; 0x00809802 nocode ; Light ; 0x00809802 nocode ; ; 0x00809802 nocode ;----------------------------------------------------------------; 0x00809802 nocode ; SCHEMATIC ; 0x00809802 nocode ; --------- ; 0x00809802 nocode ; ; 0x00809802 nocode ; C3x DSK Headers ; 0x00809802 nocode ; | TSL1402 or TSL215 ; 0x00809802 nocode ; | +--------------+ ; 0x00809802 nocode ; | | | ; 0x00809802 nocode ; VCC |--------+----------|Vdd NC| ; 0x00809802 nocode ; | | | | ; 0x00809802 nocode ; TIM1 |-------------------|SI1 S01|------+ ; 0x00809802 nocode ; | | | | | ; 0x00809802 nocode ; XF1 |-------------------|CLK GND|---+ | ; 0x00809802 nocode ; | | | | | | ; 0x00809802 nocode ; | | +-------|A01 NC| /// | ; 0x00809802 nocode ; | | | | | | ; 0x00809802 nocode ; | | | +---|GND SI2|------+ ; 0x00809802 nocode ; | | | | | | ; 0x00809802 nocode ; | | | /// |S02 NC| ; 0x00809802 nocode ; | | | | | ; 0x00809802 nocode ; | +----------|Vdd A02|----+-----+ ; 0x00809802 nocode ; AGND |---+ | | | | | | ; 0x00809802 nocode ; | | | | +--------------+ | R ; 0x00809802 nocode ; | /// | | | R 330 ; 0x00809802 nocode ; AIN+ |-----------+---------------------------+ | ; 0x00809802 nocode ; | | /// ; 0x00809802 nocode ; === Cbypass ; 0x00809802 nocode ; | ; 0x00809802 nocode ; /// ; 0x00809802 nocode ; ; 0x00809802 nocode ;****************************************************************; 0x00809802 nocode ; AIC startup values ; 0x00809802 directive TA .set 6 ; 4 ; 0x00809802 directive TB .set 12 ; 12 48*2=96 ; 0x00809802 directive RA .set 6 ; 4 ; 0x00809802 directive RB .set 12 ; 12 ; 0x00809802 directive TPRD .set 2 ; 2 ; 0x00809802 directive Hrate .set 25e6 ; DSK MIP rate ; 0x00809802 nocode ;--------------------------------------; 0x00809802 directive .include "C3XMMRS.ASM" ; 0x00809802 nocode ;-------------------------------------------------------------------- 0x00809802 nocode ; C3XMMRS.ASM 0x00809802 nocode ; Keith Larson 0x00809802 nocode ; TMS320 DSP Applications 0x00809802 nocode ; (C) Copyright 1995,1996 0x00809802 nocode ; Texas Instruments Incorporated 0x00809802 nocode ; 0x00809802 nocode ; This is unsupported freeware with no implied warranties or 0x00809802 nocode ; liabilities. See the disclaimer document for details 0x00809802 nocode ; 0x00809802 nocode ; MMR address locations for the TMS320C30 and TMS320C31 0x00809802 nocode ; 0x00809802 nocode ; Use a .include "C3XMMRS.ASM" within your application code 0x00809802 nocode ; to define the locations of the following locations 0x00809802 nocode ;-------------------------------------------------------------------- 0x00809802 directive DMA_ctrl .set 0x808000; DMA cntl 0x00809802 directive DMA_srce .set 0x808004; DMA srce address 0x00809802 directive DMA_dest .set 0x808006; DMA dest address 0x00809802 directive DMA_xfr .set 0x808008; DMA xfer counter 0x00809802 directive T0_ctrl .set 0x808020; TIM0 gl control 0x00809802 directive T0_count .set 0x808024; TIM0 count 0x00809802 directive T0_prd .set 0x808028; TIM0 prd 0x00809802 directive T1_ctrl .set 0x808030; TIM1 gl control 0x00809802 directive T1_count .set 0x808034; TIM1 count 0x00809802 directive T1_prd .set 0x808038; TIM1 prd 0x00809802 directive S0_gctrl .set 0x808040; SP 0 global control 0x00809802 directive S0_xctrl .set 0x808042; SP 0 FSX/DX/CLKX port ctl 0x00809802 directive S0_rctrl .set 0x808043; SP 0 FSR/DR/CLKR port ctl 0x00809802 directive S0_tctrl .set 0x808044; SP 0 R/X timer control 0x00809802 directive S0_tcount .set 0x808045; SP 0 R/X timer counter 0x00809802 directive S0_tprd .set 0x808046; SP 0 R/X timer period 0x00809802 directive S0_xdata .set 0x808048; SP 0 Data transmit 0x00809802 directive S0_rdata .set 0x80804C; SP 0 Data receive 0x00809802 directive S1_gctrl .set 0x808050; SP 1 global control 0x00809802 directive S1_xctrl .set 0x808052; SP 1 FSX/DX/CLKX port ctl 0x00809802 directive S1_rctrl .set 0x808053; SP 1 FSR/DR/CLKR port ctl 0x00809802 directive S1_tctrl .set 0x808054; SP 1 R/X timer control 0x00809802 directive S1_tcount .set 0x808055; SP 1 R/X timer counter 0x00809802 directive S1_tprd .set 0x808056; SP 1 R/X timer period 0x00809802 directive S1_xdata .set 0x808058; SP 1 Data transmit 0x00809802 directive S1_rdata .set 0x80805C; SP 1 Data receive 0x00809802 directive e_buscon .set 0x808060; Exp bus control 0x00809802 directive p_buscon .set 0x808064; Pri bus control 0x00809802 nocode ; 0x00809802 nocode ; Kernel functions can be accessed through the function 0x00809802 nocode ; jump table which holds the address of each function 0x00809802 nocode ; 0x00809802 directive JJUMP .set 0x809ff4 ;<- Base address 0x00809802 directive JXWRIT .set 0x809ff5 ; 0x00809802 directive JXREAD .set 0x809ff6 ; 0x00809802 directive JXCTXT .set 0x809ff7 ; 0x00809802 directive JXRUNF .set 0x809ff8 ; 0x00809802 directive JXSTEP .set 0x809ff9 ; 0x00809802 directive JXHALT .set 0x809ffA ; 0x00809802 directive JW_HOST .set 0x809ffB ; 0x00809802 directive JR_HOST .set 0x809ffC ; 0x00809802 directive JSPARE .set 0x809ffd ; 0x00809802 directive .start "AICTEST",0x809800 ; 0x00809802 directive .sect "AICTEST" ; 0x00809800 directive GIE .set 0x2000 ; 0x00809800 directive _CVTLINE .set 1 ; 0x00809800 nocode ;================================================================= 0x00809800 directive TIMERACK .word 0 ; 0x809800 0x00809800 0x00000000 0x00809801 directive A_REG .word (TA<<9)+(RA<<2)+0 ; 0x809802 0x00809801 0x00000c18 0x00809802 directive B_REG .word (TB<<9)+(RB<<2)+2 ; 0x809803 0x00809802 0x00001832 0x00809803 directive C_REG .word 01000011b ; 0x809804 +/- 6.0 V Aux 0x00809803 0x00000043 0x00809804 nocode ;-------------------------------; 0x00809804 directive PIX_DATA .word 0x809A00 ; 0x00809804 0x00809a00 0x00809805 directive S0_gctrl_val .word 0x0E970300 ; 0x00809805 0x0e970300 0x00809806 nocode ;S0_gctrl_val .word 0x0E973300 ; CLKX/R are inverted 0x00809806 directive S0_xctrl_val .word 0x00000111 ; 0x00809806 0x00000111 0x00809807 directive S0_rctrl_val .word 0x00000111 ; 0x00809807 0x00000111 0x00809808 directive T_scale .float Hrate/(4.0*1.0e6) ; Converts uS/line to C3x clocks 0x00809808 0x02480000 0x00809809 nocode ;-------------------------------; 0x00809809 0x0820804c main ldi @S0_rdata,R0 ; 0x0080980a 0x0820804c ldi @S0_rdata,R0 ; 0x0080980b 0x08299ffc ldi @JR_HOST,AR1 ; Get sub-function from host 0x0080980c 0x70000009 callu AR1 ; 0x0080980d 0x04e00001 cmpi _CVTLINE,R0 ; 0x0080980e 0x6a050003 bz CVTLINE ; 0x0080980f 0x08209870 main2 ldi @USER_RET,R0 ; 0x00809810 0x68000000 b R0 ; back to SR2 (or chain) for return 0x00809811 nocode ;****************************************************************** 0x00809811 directive Pattern .word 0x01010101 ; 0x00809811 0x01010101 0x00809812 0x08299ffc CVTLINE ldi @JR_HOST,AR1 ; 0x00809813 0x70000009 callu AR1 ; Get timer count in mS from host 0x00809814 0x05800000 float R0,R0 ; 0x00809815 0x0a209808 mpyf @T_scale,R0 ; mpyi by C3x cycles/mS 1000/40e-9 0x00809816 0x05000000 fix R0,R0 ; 0x00809817 nocode ;---------------------; 0x00809817 0x08600000 ldi 0,R0 ; 0x00809818 0x08289804 ldi @PIX_DATA,AR0 ; 0x00809819 0x087b0080 ldi 128,RC ; 0x0080981a 0x6480981c rptb Loop ; 0x0080981b 0x02209811 addi @Pattern,R0 ; 0x0080981c 0x15402001 Loop sti R0,*AR0++ ; 0x0080981d nocode ;---------------------; 0x0080981d 0x6280981f call LINECVT ; 0x0080981e 0x6a00fff0 b main2 ; return and let the host poll 0x0080981f nocode ;************************************************************* 0x0080981f 0x08289804 LINECVT ldi @PIX_DATA,AR0 ; 0x00809820 0x03770020 andn 0x20,IF ; Take care of missed RINT 0x00809821 0x6280982f call get_pix ; 0x00809822 0x6280982f call get_pix ; 0x00809823 0x087b007f ldi 127,RC ; RC = (256/2)-1 0x00809824 0x6280984d call SIpulse ; 0x00809825 nocode ;- - - - - - - - - - -; 0x00809825 0x6480982d rptb samples ; packing 2 ints per word 0x00809826 0x6280982f call get_pix ; 0x00809827 0x08020000 ldi R0,R2 ; 0x00809828 0x02e2ffff and 0xFFFF,R2 ; 0x00809829 0x6280985d call CLK ; clock the pixels 0x0080982a 0x6280982f call get_pix ; 0x0080982b nocode ; call CLK2 ; clock the pixels 0x0080982b 0x09e00010 lsh 16,R0 ; 0x0080982c 0x10000002 or R2,R0 ; 0x0080982d 0x15402001 samples sti R0,*AR0++ ; store to data array 0x0080982e 0x78800000 rets ; 0x0080982f nocode ;-------------------------------; 0x0080982f 0x083698a8 get_pix ldi @CPUINT,IE ; 0x00809830 0x10752000 Not_ADC or GIE,ST ; 0x00809831 0x08208040 ldi @S0_gctrl,R0 ; 0x00809832 0x1a600001 tstb 1,R0 ; the LSBs of S0_rdata 0x00809833 0x6a05fffc bz Not_ADC ; 0x00809834 nocode clkSRG ;---------------------; 0x00809834 0x0820804c ldi @S0_rdata,R0 ; 0x00809835 nocode ; call CLK ; clock the pixels 0x00809835 0x09e00010 lsh 16,R0 ; 0x00809836 0x03e0fff0 ash -16,R0 ; 0x00809837 0x03e0fffe ash -2,R0 ; Convert to unsigned 14 bit 0x00809838 0x02602000 addi 0x2000,R0 ; 0x00809839 0x78800000 rets ; 0x0080983a nocode ************************************************************** 0x0080983a 0x08610000 prog_AIC ldi 0,R1 ; put safe value in DXR 0x0080983b 0x15218048 sti R1,@S0_xdata ; 0x0080983c 0x06000000 idle ; 0x0080983d 0x08610003 ldi 3,R1 ; Request 2 ndy XMIT 0x0080983e 0x15218048 sti R1,@S0_xdata ; 0x0080983f 0x06000000 idle ; 0x00809840 0x15208048 sti R0,@S0_xdata ; Send register value 0x00809841 0x06000000 idle ; 0x00809842 0x08610000 ldi 0,R1 ; 0x00809843 0x15218048 sti R1,@S0_xdata ; Leave with safe value in DXR 0x00809844 0x78800000 rets ; 0x00809845 nocode ;************************************************************* 0x00809845 0x0f200000 TIM1L push R0 ; 0x00809846 0x08600002 ldi 2,R0 ; Drive TCLK1 low 0x00809847 0x6a000002 b T1RET ; 0x00809848 nocode ;----------------------; 0x00809848 0x0f200000 TIM1H push R0 ; 0x00809849 0x08600006 ldi 6,R0 ; Drive TCLK1 high 0x0080984a 0x15208030 T1RET sti R0,@T1_ctrl ; 0x0080984b 0x0e200000 pop R0 ; 0x0080984c 0x78800000 rets ; 0x0080984d nocode ;-------------------------------; 0x0080984d directive XF0L .set 0x02 ; //000000010b 0x0080984d directive XF0H .set 0x06 ; //000000110b 0x0080984d directive XF1L .set 0x20 ; //000100000b 0x0080984d directive XF1H .set 0x60 ; //001100000b 0x0080984d nocode ;-------------------------------; 0x0080984d 0x08780026 SIpulse ldi XF1L|XF0H,IOF; XF0(AIC RESET)= 1 0x0080984e 0x62809845 call TIM1L ; TIM1_----____----____--....__----____-- 0x0080984f 0x6280986e call delay ; XF1 _______----_______.....____________ 0x00809850 0x08780066 ldi XF1H|XF0H,IOF; | | 0x00809851 0x62809845 call TIM1L ; Loop B1 0x00809852 0x6280986e call delay ; Loop B1 0x00809853 0x08780066 ldi XF1H|XF0H,IOF; 0x00809854 0x62809848 call TIM1H ; 0x00809855 0x6280986e call delay ; 0x00809856 0x08780026 ldi XF1L|XF0H,IOF; 0x00809857 0x62809848 call TIM1H ; 0x00809858 0x6280986e call delay ; 0x00809859 0x08780026 ldi XF1L|XF0H,IOF; 0x0080985a 0x62809845 call TIM1L ; 0x0080985b 0x6280986e call delay ; 0x0080985c 0x78800000 rets ; 0x0080985d nocode ;----------------------; 0x0080985d 0x08780026 CLK ldi XF1L|XF0H,IOF; 0x0080985e 0x62809848 call TIM1H ; 0x0080985f 0x6280986e call delay ; 0x00809860 0x08780026 ldi XF1L|XF0H,IOF; 0x00809861 0x62809845 call TIM1L ; 0x00809862 0x6280986e call delay ; 0x00809863 0x78800000 rets ; 0x00809864 nocode ;----------------------; 0x00809864 0x08780026 CLK2 ldi XF1L|XF0H,IOF; 0x00809865 0x62809845 call TIM1L ; 0x00809866 0x6280986e call delay ; 0x00809867 0x08780026 ldi XF1L|XF0H,IOF; 0x00809868 0x62809848 call TIM1H ; 0x00809869 0x6280986e call delay ; 0x0080986a 0x78800000 rets ; 0x0080986b nocode ;-------------------------------; 0x0080986b 0x6280986c call $+1 ; 60 15 (1+2+3+4+5)*4 0x0080986c 0x6280986d call $+1 ; 40 10 (1+2+3+4 )*4 0x0080986d 0x6280986e call $+1 ; 24 6 (1+2+3 )*4 0x0080986e 0x6280986f delay call $+1 ; 12 3 (1+2 )*4 0x0080986f 0x78800000 D8 rets ; 4 1 (1 )*4 0x00809870 nocode ;*****************************************************; 0x00809870 nocode ; Startup stub... ; 0x00809870 nocode ; ; 0x00809870 nocode ; The following section of code is used only once for ; 0x00809870 nocode ; initialization and can be safely overwritten by ; 0x00809870 nocode ; assembling it into the stack or volatile data ; 0x00809870 nocode ; storage. ; 0x00809870 nocode ;*****************************************************; 0x00809870 directive USER_RET .word 0 ; 0x00809870 0x00000000 0x00809871 directive .entry ST_STUB ; 0x00809871 directive XSPARE .word main ; 0x00809871 0x00809809 0x00809872 0x50700080 ST_STUB ldp T0_ctrl ; Use kernel data page and stack 0x00809873 0x08209ffd ldi @JSPARE,R0 ; 0x00809874 0x15209870 sti R0,@USER_RET ; 0x00809875 0x08209871 ldi @XSPARE,R0 ; 0x00809876 0x15209ffd sti R0,@JSPARE ; 0x00809877 0x08600000 ldi 0,R0 ; Halt TIM0 & TIM1 0x00809878 0x15208020 sti R0,@T0_ctrl ; 0x00809879 0x15208024 sti R0,@T0_count ; count 0x0080987a 0x08600002 ldi TPRD,R0 ; period 0x0080987b 0x15208028 sti R0,@T0_prd ; 0x0080987c 0x08600064 ldi 100,R0 ; 0x0080987d 0x086003c1 ldi 0x3C1,R0 ; Restart both timers 0x0080987e 0x15208020 sti R0,@T0_ctrl ; 0x0080987f nocode ;=====================================================; 0x0080987f nocode ; This section of code initializes the AIC ; 0x0080987f nocode ;=====================================================; 0x0080987f 0x08209806 ldi @S0_xctrl_val,R0; 0x00809880 0x15208042 sti R0,@S0_xctrl ; transmit control 0x00809881 0x08209807 ldi @S0_rctrl_val,R0; 0x00809882 0x15208043 sti R0,@S0_rctrl ; receive control 0x00809883 0x08600000 ldi 0,R0 ; 0x00809884 0x15208048 sti R0,@S0_xdata ; DXR data value 0x00809885 0x08209805 ldi @S0_gctrl_val,R0; Setup serial port 0x00809886 0x15208040 sti R0,@S0_gctrl ; global control 0x00809887 nocode ;---------------------; 0x00809887 0x08760010 AIC_INIT LDI 0x10,IE ; Enable only XINT interrupt 0x00809888 0x08600000 ldi 0,R0 ; 0x00809889 0x15208048 sti R0,@S0_xdata ; 0x0080988a 0x13fb0040 RPTS 0x040 ; 0x0080988b 0x08780002 LDI 2,IOF ; XF0=0 resets AIC 0x0080988c 0x13fb0040 rpts 0x40 ; 0x0080988d 0x08780006 LDI 6,IOF ; XF0=1 runs AIC 0x0080988e nocode ;---------------------; 0x0080988e 0x08209803 ldi @C_REG,R0 ; Setup control register 0x0080988f 0x6280983a call prog_AIC ; 0x00809890 0x08209802 ldi @B_REG,R0 ; Bump up the Fs to final rate 0x00809891 0x6280983a call prog_AIC ; (smallest divisor should be last) 0x00809892 0x08209801 ldi @A_REG,R0 ; 0x00809893 0x6280983a call prog_AIC ; 0x00809894 nocode ;--------------------- 0x00809894 0x0820804c ldi @S0_rdata,R0 ; Fix the receiver underrun by reading 0x00809895 0x082098ab ldi @buscon,R0 ; 0x00809896 0x15208064 sti R0,@p_buscon ; 0x00809897 0x08600000 ldi 0,R0 ; 0x00809898 0x15208048 sti R0,@S0_xdata ; 0x00809899 0x082098a9 DMAsetup ldi @SRCEX,R0 ; start DMA... 0x0080989a 0x15208004 sti R0,@DMA_srce ; ADC->S0_rdata 0x0080989b 0x082098aa ldi @DESTX,R0 ; 0x0080989c 0x15208006 sti R0,@DMA_dest ; 0x0080989d 0x0860000b ldi 11,R0 ; Any count value works 0x0080989e 0x15208008 sti R0,@DMA_xfr ; 0x0080989f nocode ; ldi 0x103,R0 ; Transfer on dma_interrupt.. Source synch 0x0080989f 0x08600003 ldi 0x003,R0 ; Always write.. No synch 0x008098a0 0x15208000 sti R0,@DMA_ctrl ; 0x008098a1 nocode ;- - - - - - - - - - -; 0x008098a1 0x083498ac ldi @U_stack,SP ; 0x008098a2 0x08600000 ldi 0,R0 ; 0x008098a3 0x15208048 sti R0,@S0_xdata ; 0x008098a4 0x083698a8 Spin1 ldi @CPUINT,IE ; 0x008098a5 0x10760204 or 0x204,IE ; Enable TINT_1 and INT_2 0x008098a6 0x10752000 or GIE,ST ; 0x008098a7 0x6a00fffc b Spin1 ; Except for debug, this is now spin0 0x008098a8 nocode ;-------------------------------; 0x008098a8 directive CPUINT .word 0x00100020 ; XINT0_DMA RINT0_CPU 0x008098a8 0x00100020 0x008098a9 directive SRCEX .word S0_rdata ; 0x008098a9 0x0080804c 0x008098aa directive DESTX .word S0_xdata ; 0x008098aa 0x00808048 0x008098ab directive buscon .word 0x000010F8 ; 0x008098ab 0x000010f8 0x008098ac directive U_stack .word $ ; 0x008098ac 0x008098ac 0x008098ad nocode ;*****************************************************; 0x008098ad nocode ; Install the XINT/RINT ISR handler directly into ; 0x008098ad nocode ; the vector RAM location it will be used in ; 0x008098ad nocode ;*****************************************************; 0x008098ad directive .start "SP0VECTS",0x809FC5 0x008098ad directive .sect "SP0VECTS" ; 0x00809fc5 0x78000000 reti ; XINT0 (AIC_2ndy or DMA) 0x00809fc6 0x78000000 reti ; RINT0 0x00809fc7 directive .start "T1VECTS",0x809FCA 0x00809fc7 directive .sect "T1VECTS" ; 0x00809fca 0x78000000 reti ; 0x00809fcb directive .end ; >>>> >>>> PASS 2 Complete >>>> Errors: 0 Warnings: 0 >>>> >>>> ENTRY 0x00809872 >>>> >>>> Symbol reference table Type Addressable >>>> ref Default_sect 0x00809802 1 1 >>>> ref TA 0x00000006 1 0 >>>> ref TB 0x0000000c 1 0 >>>> ref RA 0x00000006 1 0 >>>> ref RB 0x0000000c 1 0 >>>> ref TPRD 0x00000002 1 0 >>>> ref Hrate 0x4bbebc20 2 0 >>>> ref DMA_ctrl 0x00808000 1 0 >>>> ref DMA_srce 0x00808004 1 0 >>>> ref DMA_dest 0x00808006 1 0 >>>> ref DMA_xfr 0x00808008 1 0 >>>> ref T0_ctrl 0x00808020 1 0 >>>> ref T0_count 0x00808024 1 0 >>>> ref T0_prd 0x00808028 1 0 >>>> ref T1_ctrl 0x00808030 1 0 >>>> ref T1_count 0x00808034 1 0 >>>> ref T1_prd 0x00808038 1 0 >>>> ref S0_gctrl 0x00808040 1 0 >>>> ref S0_xctrl 0x00808042 1 0 >>>> ref S0_rctrl 0x00808043 1 0 >>>> ref S0_tctrl 0x00808044 1 0 >>>> ref S0_tcount 0x00808045 1 0 >>>> ref S0_tprd 0x00808046 1 0 >>>> ref S0_xdata 0x00808048 1 0 >>>> ref S0_rdata 0x0080804c 1 0 >>>> ref S1_gctrl 0x00808050 1 0 >>>> ref S1_xctrl 0x00808052 1 0 >>>> ref S1_rctrl 0x00808053 1 0 >>>> ref S1_tctrl 0x00808054 1 0 >>>> ref S1_tcount 0x00808055 1 0 >>>> ref S1_tprd 0x00808056 1 0 >>>> ref S1_xdata 0x00808058 1 0 >>>> ref S1_rdata 0x0080805c 1 0 >>>> ref e_buscon 0x00808060 1 0 >>>> ref p_buscon 0x00808064 1 0 >>>> ref JJUMP 0x00809ff4 1 0 >>>> ref JXWRIT 0x00809ff5 1 0 >>>> ref JXREAD 0x00809ff6 1 0 >>>> ref JXCTXT 0x00809ff7 1 0 >>>> ref JXRUNF 0x00809ff8 1 0 >>>> ref JXSTEP 0x00809ff9 1 0 >>>> ref JXHALT 0x00809ffa 1 0 >>>> ref JW_HOST 0x00809ffb 1 0 >>>> ref JR_HOST 0x00809ffc 1 0 >>>> ref JSPARE 0x00809ffd 1 0 >>>> ref AICTEST 0x00809800 1 1 >>>> ref GIE 0x00002000 1 0 >>>> ref _CVTLINE 0x00000001 1 0 >>>> ref TIMERACK 0x00809800 1 1 >>>> ref A_REG 0x00809801 1 1 >>>> ref B_REG 0x00809802 1 1 >>>> ref C_REG 0x00809803 1 1 >>>> ref PIX_DATA 0x00809804 1 1 >>>> ref S0_gctrl_val 0x00809805 1 1 >>>> ref S0_xctrl_val 0x00809806 1 1 >>>> ref S0_rctrl_val 0x00809807 1 1 >>>> ref T_scale 0x00809808 2 1 >>>> ref main 0x00809809 1 1 >>>> ref main2 0x0080980f 1 1 >>>> ref Pattern 0x00809811 1 1 >>>> ref CVTLINE 0x00809812 1 1 >>>> ref Loop 0x0080981c 1 1 >>>> ref LINECVT 0x0080981f 1 1 >>>> ref samples 0x0080982d 1 1 >>>> ref get_pix 0x0080982f 1 1 >>>> ref Not_ADC 0x00809830 1 1 >>>> ref clkSRG 0x00809834 1 1 >>>> ref prog_AIC 0x0080983a 1 1 >>>> ref TIM1L 0x00809845 1 1 >>>> ref TIM1H 0x00809848 1 1 >>>> ref T1RET 0x0080984a 1 1 >>>> ref XF0L 0x00000002 1 0 >>>> ref XF0H 0x00000006 1 0 >>>> ref XF1L 0x00000020 1 0 >>>> ref XF1H 0x00000060 1 0 >>>> ref SIpulse 0x0080984d 1 1 >>>> ref CLK 0x0080985d 1 1 >>>> ref CLK2 0x00809864 1 1 >>>> ref delay 0x0080986e 1 1 >>>> ref D8 0x0080986f 1 1 >>>> ref USER_RET 0x00809870 1 1 >>>> ref XSPARE 0x00809871 1 1 >>>> ref ST_STUB 0x00809872 1 1 >>>> ref AIC_INIT 0x00809887 1 1 >>>> ref DMAsetup 0x00809899 1 1 >>>> ref Spin1 0x008098a4 1 1 >>>> ref CPUINT 0x008098a8 1 1 >>>> ref SRCEX 0x008098a9 1 1 >>>> ref DESTX 0x008098aa 1 1 >>>> ref buscon 0x008098ab 1 1 >>>> ref U_stack 0x008098ac 1 1 >>>> ref SP0VECTS 0x00809fc5 1 1 >>>> ref T1VECTS 0x00809fca 1 1 >>>> >>>> Output section start end length >>>> sect Default_sect 0x00809802 0x00809802 0x00000000 >>>> sect AICTEST 0x00809800 0x008098ad 0x000000ad >>>> sect SP0VECTS 0x00809fc5 0x00809fc7 0x00000002 >>>> sect T1VECTS 0x00809fca 0x00809fcb 0x00000001 >>>> >>>> >>>> END DSK