>>>> DSK3A C3x DSP Starter Kit Assembler Rev 1.17 >>>> (c) Copyright 1994-1995 Texas Instruments Incorporated >>>> Mon Oct 27 11:03:04 1997 >>>> LOOPAIC.ASM >>>> >>>> >>>> PASS 1 Complete >>>> Errors: 0 Warnings: 0 >>>> 0x00809802 nocode ;------------------------------------------------------------------------- 0x00809802 nocode ; LOOPAIC.ASM 0x00809802 nocode ; Keith Larson 0x00809802 nocode ; TMS320 DSP Applications 0x00809802 nocode ; (C) Copyright 1995,1996 0x00809802 nocode ; Texas Instruments Incorporated 0x00809802 nocode ; 0x00809802 nocode ; This is unsupported freeware with no implied warranties or 0x00809802 nocode ; liabilities. See the disclaimer document for details 0x00809802 nocode ; 0x00809802 nocode ; LOOPAIC.ASM is a simple program which initializes and uses the TLC32040. 0x00809802 nocode ; The analog ADC input is either looped back to to the DAC output (RAMPEN=0) 0x00809802 nocode ; or a sawtooth ramp is generated at the DAC output (RAMPEN=1). 0x00809802 nocode ;------------------------------------------------------------------------- 0x00809802 directive .start "AICTEST",0x809802 ; Start assembling here 0x00809802 directive .sect "AICTEST" ; 0x00809802 nocode ;------------------------------------ 0x00809802 nocode ; Define constants used by program 0x00809802 nocode ;------------------------------------ 0x00809802 directive RAMPEN .set 0 ; Set to 1 to generate ramp at AOUT 0x00809802 directive T0_ctrl .set 0x808020 ; TIM0 gl control 0x00809802 directive T0_count .set 0x808024 ; TIM0 count 0x00809802 directive T0_prd .set 0x808028 ; TIM0 prd 0x00809802 directive S0_gctrl .set 0x808040 ; SP 0 global control 0x00809802 directive S0_xctrl .set 0x808042 ; SP 0 FSX/DX/CLKX port ctl 0x00809802 directive S0_rctrl .set 0x808043 ; SP 0 FSR/DR/CLKR port ctl 0x00809802 directive S0_xdata .set 0x808048 ; SP 0 Data transmit 0x00809802 directive S0_rdata .set 0x80804C ; SP 0 Data receive 0x00809802 directive TIM0_PRD .set 2 ; Timer diviser 0x00809802 directive TA .set 8 ; AIC timing register values 0x00809802 directive TB .set 14 ; 0x00809802 directive RA .set 8 ; 0x00809802 directive RB .set 14 ; 0x00809802 directive GIE .set 0x2000 ; This bit in ST turns on interrupts 0x00809802 nocode ;------------------------------------ 0x00809802 nocode ; Define some constant storage data 0x00809802 nocode ;------------------------------------ 0x00809802 directive A_REG .word (TA<<9)+(RA<<2)+0 ; A registers 0x00809802 0x00001020 0x00809803 directive B_REG .word (TB<<9)+(RB<<2)+2 ; B registers 0x00809803 0x00001c3a 0x00809804 directive C_REG .word 00000011b ; control 0x00809804 0x00000003 0x00809805 directive S0_gctrl_val .word 0x0E970300 ; Serial port control register values 0x00809805 0x0e970300 0x00809806 directive S0_xctrl_val .word 0x00000111 ; 0x00809806 0x00000111 0x00809807 directive S0_rctrl_val .word 0x00000111 ; 0x00809807 0x00000111 0x00809808 directive RAMP .word 0 ; RAMP count value 0x00809808 0x00000000 0x00809809 directive ADC_last .word 0 ; Last received ADC value 0x00809809 0x00000000 0x0080980a nocode ;**************************************************** 0x0080980a nocode ; Begin main code loop here 0x0080980a nocode ;**************************************************** 0x0080980a 0x10752000 main or GIE,ST ; Turn on INTS 0x0080980b 0x087600f4 ldi 0xF4,IE ; Enable XINT/RINT/INT2 0x0080980c 0x6a00fffd b main ; Do it again! 0x0080980d nocode ;------------------------------- 0x0080980d 0x0f350000 DAC2 push ST ; DAC Interrupt service routine 0x0080980e 0x0f230000 push R3 ; 0x0080980f directive .if RAMPEN ; If RAMPEN=1 assemble this code 0x0080980f if_off ldi @RAMP,R3 ; 0x0080980f if_off addi 256,R3 ; Add a value to RAMP 0x0080980f if_off sti R3,@RAMP ; 0x0080980f directive .else ; Else assemble this 0x0080980f 0x08239809 ldi @ADC_last,R3 ; 0x00809810 nocode ; mpyi 1,R3 ; Scale up the ADC value to see distortion 0x00809810 0x04e37fff cmpi 32767,R3 ; 0x00809811 0x54e37fff ldigt 32767,R3 ; 0x00809812 0x04e38000 cmpi -32768,R3 ; 0x00809813 0x53e38000 ldilt -32768,R3 ; 0x00809814 directive .endif ; 0x00809814 0x03630003 andn 3,R3 ; 0x00809815 0x15238048 sti R3,@S0_xdata ; Output the new DAC value 0x00809816 0x0e230000 pop R3 ; 0x00809817 0x0e350000 pop ST ; 0x00809818 0x78000000 reti ; 0x00809819 nocode ;------------------------------- 0x00809819 0x0f350000 ADC2 push ST ; 0x0080981a 0x0f230000 push R3 ; 0x0080981b 0x0823804c ldi @S0_rdata,R3 ; Sign extend the data 0x0080981c 0x09e30010 lsh 16,R3 ;SEE NOTE; Present data is in lower 16 bits 0x0080981d 0x03e3fff0 ash -16,R3 ; >> Sample N-1 is in upper 16 bits 0x0080981e 0x15239809 sti R3,@ADC_last ; If a delay is acceptable, the 'LSH 11,R3' 0x0080981f 0x0e230000 pop R3 ; can be ommitted 0x00809820 0x0e350000 pop ST ; 0x00809821 0x78000000 reti ; 0x00809822 nocode ;*****************************************************; 0x00809822 nocode ; The startup stub is used during initialization only ; 0x00809822 nocode ; and can be safely overwritten by the stack or data ; 0x00809822 nocode ;*****************************************************; 0x00809822 directive .entry ST_STUB ; Debugger starts here 0x00809822 0x50700080 ST_STUB ldp T0_ctrl ; Use kernel data page and stack 0x00809823 0x08349853 ldi @stack,SP 0x00809824 0x08600000 ldi 0,R0 ; Halt TIM0 0x00809825 0x15208020 sti R0,@T0_ctrl ; 0x00809826 0x15208024 sti R0,@T0_count ; Zero the count 0x00809827 0x08600002 ldi TIM0_PRD,R0 ; Set the period 0x00809828 0x15208028 sti R0,@T0_prd ; 0x00809829 0x086002c1 ldi 0x2C1,R0 ; Restart the timer 0x0080982a 0x15208020 sti R0,@T0_ctrl ; 0x0080982b nocode ;--------------------- 0x0080982b 0x08209806 ldi @S0_xctrl_val,R0; 0x0080982c 0x15208042 sti R0,@S0_xctrl ; transmit control 0x0080982d 0x08209807 ldi @S0_rctrl_val,R0; 0x0080982e 0x15208043 sti R0,@S0_rctrl ; receive control 0x0080982f 0x08600000 ldi 0,R0 ; 0x00809830 0x15208048 sti R0,@S0_xdata ; DXR data value 0x00809831 0x08209805 ldi @S0_gctrl_val,R0; Setup serial port 0x00809832 0x15208040 sti R0,@S0_gctrl ; global control 0x00809833 nocode ;======================================================; 0x00809833 nocode ; This section of code initializes the AIC ; 0x00809833 nocode ;======================================================; 0x00809833 0x08760010 AIC_INIT LDI 0x10,IE ; Enable only XINT interrupt 0x00809834 0x03770034 andn 0x34,IF ; 0x00809835 0x08600000 ldi 0,R0 ; 0x00809836 0x15208048 sti R0,@S0_xdata ; 0x00809837 0x13fb0040 RPTS 0x040 ; 0x00809838 0x08780002 LDI 2,IOF ; XF0=0 resets AIC 0x00809839 0x13fb0040 rpts 0x40 ; 0x0080983a 0x08780006 LDI 6,IOF ; XF0=1 runs AIC 0x0080983b nocode ;--------------------- 0x0080983b 0x08209804 ldi @C_REG,R0 ; Setup control register 0x0080983c 0x62809846 call prog_AIC ; 0x0080983d 0x0860fffc ldi 0xfffc ,R0 ; Program the AIC to be real slow 0x0080983e 0x62809846 call prog_AIC ; 0x0080983f 0x0860fffe ldi 0xfffc|2,R0 ; 0x00809840 0x62809846 call prog_AIC ; 0x00809841 0x08209803 ldi @B_REG,R0 ; Bump up the Fs to final rate 0x00809842 0x62809846 call prog_AIC ; (smallest divisor should be last) 0x00809843 0x08209802 ldi @A_REG,R0 ; 0x00809844 0x62809846 call prog_AIC ; 0x00809845 0x6a00ffc4 b main ; 0x00809846 nocode ;------------------------------- 0x00809846 0x08218048 prog_AIC ldi @S0_xdata,R1 ; Use original DXR data during 2 ndy 0x00809847 0x15218048 sti R1,@S0_xdata ; 0x00809848 0x06000000 idle 0x00809849 0x08218048 ldi @S0_xdata,R1 ; Use original DXR data during 2 ndy 0x0080984a 0x10610003 or 3,R1 ; Request 2 ndy XMIT 0x0080984b 0x15218048 sti R1,@S0_xdata ; 0x0080984c 0x06000000 idle ; 0x0080984d 0x15208048 sti R0,@S0_xdata ; Send register value 0x0080984e 0x06000000 idle ; 0x0080984f 0x03610003 andn 3,R1 ; 0x00809850 0x15218048 sti R1,@S0_xdata ; Leave with original safe value in DXR 0x00809851 nocode ;--------------------- 0x00809851 0x0820804c ldi @S0_rdata,R0 ; Fix the receiver underrun by reading 0x00809852 0x78800000 rets ; the DRR before going to the main loop 0x00809853 directive stack .word $ ; Put stack here 0x00809853 0x00809853 0x00809854 nocode ;****************************************************; 0x00809854 nocode ; Install the XINT/RINT ISR handler directly into ; 0x00809854 nocode ; the vector RAM location it will be used for ; 0x00809854 nocode ;****************************************************; 0x00809854 directive .start "SP0VECTS",0x809FC5 0x00809854 directive .sect "SP0VECTS" 0x00809fc5 0x6a00f847 B DAC2 ; XINT0 0x00809fc6 0x6a00f852 B ADC2 ; RINT0 >>>> >>>> PASS 2 Complete >>>> Errors: 0 Warnings: 0 >>>> >>>> ENTRY 0x00809822 >>>> >>>> Symbol reference table Type Addressable >>>> ref Default_sect 0x00809802 1 1 >>>> ref AICTEST 0x00809802 1 1 >>>> ref RAMPEN 0x00000000 1 0 >>>> ref T0_ctrl 0x00808020 1 0 >>>> ref T0_count 0x00808024 1 0 >>>> ref T0_prd 0x00808028 1 0 >>>> ref S0_gctrl 0x00808040 1 0 >>>> ref S0_xctrl 0x00808042 1 0 >>>> ref S0_rctrl 0x00808043 1 0 >>>> ref S0_xdata 0x00808048 1 0 >>>> ref S0_rdata 0x0080804c 1 0 >>>> ref TIM0_PRD 0x00000002 1 0 >>>> ref TA 0x00000008 1 0 >>>> ref TB 0x0000000e 1 0 >>>> ref RA 0x00000008 1 0 >>>> ref RB 0x0000000e 1 0 >>>> ref GIE 0x00002000 1 0 >>>> ref A_REG 0x00809802 1 1 >>>> ref B_REG 0x00809803 1 1 >>>> ref C_REG 0x00809804 1 1 >>>> ref S0_gctrl_val 0x00809805 1 1 >>>> ref S0_xctrl_val 0x00809806 1 1 >>>> ref S0_rctrl_val 0x00809807 1 1 >>>> ref RAMP 0x00809808 1 1 >>>> ref ADC_last 0x00809809 1 1 >>>> ref main 0x0080980a 1 1 >>>> ref DAC2 0x0080980d 1 1 >>>> ref ADC2 0x00809819 1 1 >>>> ref ST_STUB 0x00809822 1 1 >>>> ref AIC_INIT 0x00809833 1 1 >>>> ref prog_AIC 0x00809846 1 1 >>>> ref stack 0x00809853 1 1 >>>> ref SP0VECTS 0x00809fc5 1 1 >>>> >>>> Output section start end length >>>> sect Default_sect 0x00809802 0x00809802 0x00000000 >>>> sect AICTEST 0x00809802 0x00809854 0x00000052 >>>> sect SP0VECTS 0x00809fc5 0x00809fc7 0x00000002 >>>> >>>> >>>> END DSK