>>>> DSK3A C3x DSP Starter Kit Assembler Rev 1.17 >>>> (c) Copyright 1994-1995 Texas Instruments Incorporated >>>> Fri Sep 26 09:51:59 1997 >>>> CHI.ASM >>>> >>>> Include Open : C3XMMRS.ASM >>>> Include Close: C3XMMRS.ASM >>>> >>>> PASS 1 Complete >>>> Errors: 0 Warnings: 0 >>>> 0x00809802 nocode ;--------------------------------------------------------- 0x00809802 nocode ; FIR.ASM 0x00809802 nocode ; Keith Larson 0x00809802 nocode ; TMS320 DSP Applications 0x00809802 nocode ; (C) Copyright 1995,1996 0x00809802 nocode ; Texas Instruments Incorporated 0x00809802 nocode ; 0x00809802 nocode ; This is unsupported freeware with no implied warranties or 0x00809802 nocode ; liabilities. See the disclaimer document for details 0x00809802 nocode ; 0x00809802 nocode ; The FIR filter code used in this example is taken 0x00809802 nocode ; from the TMS320C3x Users Guide. The AIC setup and 0x00809802 nocode ; control is designed to work with the TMS320C31 DSK 0x00809802 nocode ; 0x00809802 nocode ; This example can either be loaded and run from the debugger 0x00809802 nocode ; or by directly loading and running from DSK3LOAD 0x00809802 nocode ;--------------------------------------------------------- 0x00809802 nocode ; Define constants used by program ; 0x00809802 directive TA .set 8 ; AIC timing register values 0x00809802 directive TB .set 16 ; 0x00809802 directive RA .set 8 ; 0x00809802 directive RB .set 16 ; 0x00809802 directive GIE .set 0x2000 ; This bit in ST turns on interrupts 0x00809802 directive .include "C3XMMRS.ASM" ; 0x00809802 nocode ;-------------------------------------------------------------------- 0x00809802 nocode ; C3XMMRS.ASM 0x00809802 nocode ; Keith Larson 0x00809802 nocode ; TMS320 DSP Applications 0x00809802 nocode ; (C) Copyright 1995,1996 0x00809802 nocode ; Texas Instruments Incorporated 0x00809802 nocode ; 0x00809802 nocode ; This is unsupported freeware with no implied warranties or 0x00809802 nocode ; liabilities. See the disclaimer document for details 0x00809802 nocode ; 0x00809802 nocode ; MMR address locations for the TMS320C30 and TMS320C31 0x00809802 nocode ; 0x00809802 nocode ; Use a .include "C3XMMRS.ASM" within your application code 0x00809802 nocode ; to define the locations of the following locations 0x00809802 nocode ;-------------------------------------------------------------------- 0x00809802 directive DMA_ctrl .set 0x808000; DMA cntl 0x00809802 directive DMA_srce .set 0x808004; DMA srce address 0x00809802 directive DMA_dest .set 0x808006; DMA dest address 0x00809802 directive DMA_xfr .set 0x808008; DMA xfer counter 0x00809802 directive T0_ctrl .set 0x808020; TIM0 gl control 0x00809802 directive T0_count .set 0x808024; TIM0 count 0x00809802 directive T0_prd .set 0x808028; TIM0 prd 0x00809802 directive T1_ctrl .set 0x808030; TIM1 gl control 0x00809802 directive T1_count .set 0x808034; TIM1 count 0x00809802 directive T1_prd .set 0x808038; TIM1 prd 0x00809802 directive S0_gctrl .set 0x808040; SP 0 global control 0x00809802 directive S0_xctrl .set 0x808042; SP 0 FSX/DX/CLKX port ctl 0x00809802 directive S0_rctrl .set 0x808043; SP 0 FSR/DR/CLKR port ctl 0x00809802 directive S0_tctrl .set 0x808044; SP 0 R/X timer control 0x00809802 directive S0_tcount .set 0x808045; SP 0 R/X timer counter 0x00809802 directive S0_tprd .set 0x808046; SP 0 R/X timer period 0x00809802 directive S0_xdata .set 0x808048; SP 0 Data transmit 0x00809802 directive S0_rdata .set 0x80804C; SP 0 Data receive 0x00809802 directive S1_gctrl .set 0x808050; SP 1 global control 0x00809802 directive S1_xctrl .set 0x808052; SP 1 FSX/DX/CLKX port ctl 0x00809802 directive S1_rctrl .set 0x808053; SP 1 FSR/DR/CLKR port ctl 0x00809802 directive S1_tctrl .set 0x808054; SP 1 R/X timer control 0x00809802 directive S1_tcount .set 0x808055; SP 1 R/X timer counter 0x00809802 directive S1_tprd .set 0x808056; SP 1 R/X timer period 0x00809802 directive S1_xdata .set 0x808058; SP 1 Data transmit 0x00809802 directive S1_rdata .set 0x80805C; SP 1 Data receive 0x00809802 directive e_buscon .set 0x808060; Exp bus control 0x00809802 directive p_buscon .set 0x808064; Pri bus control 0x00809802 nocode ; 0x00809802 nocode ; Kernel functions can be accessed through the function 0x00809802 nocode ; jump table which holds the address of each function 0x00809802 nocode ; 0x00809802 directive JJUMP .set 0x809ff4 ;<- Base address 0x00809802 directive JXWRIT .set 0x809ff5 ; 0x00809802 directive JXREAD .set 0x809ff6 ; 0x00809802 directive JXCTXT .set 0x809ff7 ; 0x00809802 directive JXRUNF .set 0x809ff8 ; 0x00809802 directive JXSTEP .set 0x809ff9 ; 0x00809802 directive JXHALT .set 0x809ffA ; 0x00809802 directive JW_HOST .set 0x809ffB ; 0x00809802 directive JR_HOST .set 0x809ffC ; 0x00809802 directive JSPARE .set 0x809ffd ; 0x00809802 directive .start "AICTEST",0x809820 ; Start assembling here 0x00809802 directive .sect "AICTEST" ; 0x00809820 nocode ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0x00809820 nocode ; 32 bit float data buffer of incoming data from the AIC 0x00809820 nocode ; The location in memory must be on a 2^N boundary and the 0x00809820 nocode ; size of the coefficeint table must be the same as the data 0x00809820 nocode ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0x00809820 directive ADC_recv .float 0.0 ; 0x00809820 0x80000000 0x00809821 directive .float 0.0 ; 0x00809821 0x80000000 0x00809822 directive .float 0.0 ; 0x00809822 0x80000000 0x00809823 directive .float 0.0 ; 0x00809823 0x80000000 0x00809824 directive .float 0.0 ; 0x00809824 0x80000000 0x00809825 directive .float 0.0 ; 0x00809825 0x80000000 0x00809826 directive .float 0.0 ; 0x00809826 0x80000000 0x00809827 directive .float 0.0 ; 0x00809827 0x80000000 0x00809828 directive .float 0.0 ; 0x00809828 0x80000000 0x00809829 directive .float 0.0 ; 0x00809829 0x80000000 0x0080982a directive .float 0.0 ; 0x0080982a 0x80000000 0x0080982b directive .float 0.0 ; 0x0080982b 0x80000000 0x0080982c directive .float 0.0 ; 0x0080982c 0x80000000 0x0080982d directive .float 0.0 ; 0x0080982d 0x80000000 0x0080982e directive .float 0.0 ; 0x0080982e 0x80000000 0x0080982f directive .float 0.0 ; 0x0080982f 0x80000000 0x00809830 nocode ;- - - - - - - - - - - - - - - - - - - - - - - - - 0x00809830 nocode ; FIR filter coefficients 0x00809830 nocode ;- - - - - - - - - - - - - - - - - - - - - - - - - 0x00809830 directive FIR_coef .float 1.0 ; FIR filter coefficients 0x00809830 0x00000000 0x00809831 directive .float 0.0 ; 0x00809831 0x80000000 0x00809832 directive .float 0.0 ; 0x00809832 0x80000000 0x00809833 directive .float 0.0 ; 0x00809833 0x80000000 0x00809834 directive .float 0.0 ; As is, these coefficients will create 0x00809834 0x80000000 0x00809835 directive .float 0.0 ; a comb filter at Hz. By inspection 0x00809835 0x80000000 0x00809836 directive .float 0.0 ; all taps are zero except for the 0th 0x00809836 0x80000000 0x00809837 directive .float 0.0 ; and 15th that are set to 1 and -1 0x00809837 0x80000000 0x00809838 directive .float 0.0 ; respectively. Therefor a cancellation 0x00809838 0x80000000 0x00809839 directive .float 0.0 ; will occur for any signal which is 0x00809839 0x80000000 0x0080983a directive .float 0.0 ; 180' out of phase when delayed by 0x0080983a 0x80000000 0x0080983b directive .float 0.0 ; 15 samples. The Z transform is... 0x0080983b 0x80000000 0x0080983c directive .float 0.0 ; 0x0080983c 0x80000000 0x0080983d directive .float 0.0 ; 0x0080983d 0x80000000 0x0080983e directive .float 0.0 ; -15 0x0080983e 0x80000000 0x0080983f directive .float -1.0 ; H(z)=1-z 0x0080983f 0xff800000 0x00809840 nocode END_coef 0x00809840 nocode ;- - - - - - - - - - - - - - - - - - - 0x00809840 directive BufSz .set END_coef - FIR_coef 0x00809840 nocode ;- - - - - - - - - - - - - - - - - - - 0x00809840 directive SIZE .word BufSz ; Size of filter 0x00809840 0x00000010 0x00809841 directive ADC_first .word ADC_recv 0x00809841 0x00809820 0x00809842 directive ADC_end .word FIR_coef 0x00809842 0x00809830 0x00809843 directive ADC_last .word ADC_recv 0x00809843 0x00809820 0x00809844 directive FIR_coefx .word FIR_coef 0x00809844 0x00809830 0x00809845 nocode ;------------------------------------ 0x00809845 nocode ; Define some constant storage data 0x00809845 nocode ;------------------------------------ 0x00809845 directive A_REG .word (TA<<9)+(RA<<2)+0 ; A registers 0x00809845 0x00001020 0x00809846 directive B_REG .word (TB<<9)+(RB<<2)+2 ; B registers 0x00809846 0x00002042 0x00809847 directive C_REG .word 00000011b ; control 0x00809847 0x00000003 0x00809848 directive S0_gctrl_val .word 0x0E970300 ; Serial port control register values 0x00809848 0x0e970300 0x00809849 directive S0_xctrl_val .word 0x00000111 ; 0x00809849 0x00000111 0x0080984a directive S0_rctrl_val .word 0x00000111 ; 0x0080984a 0x00000111 0x0080984b nocode ;**************************************************** 0x0080984b nocode ; Begin main code loop here 0x0080984b nocode ;**************************************************** 0x0080984b directive .entry main 0x0080984b nocode main ;or GIE,ST ; Turn on INTS 0x0080984b 0x08689c77 ldi 09c77h,ar0 0x0080984c 0x08699c77 ldi 09c77h,ar1 0x0080984d 0x02e8ffff and 0ffffh,ar0 0x0080984e 0x02e9ffff and 0ffffh,ar1 0x0080984f 0x106a9c77 or 09c77h,ar2 0x00809850 0x106b9000 or 09000h,ar3 0x00809851 0x106c9c77 or 09c77h,ar4 0x00809852 0x106d9c77 or 09c77h,ar5 0x00809853 0x106e9c77 or 09c77h,ar6 0x00809854 0x106f9c77 or 09c77h,ar7 0x00809855 0x08700000 ldi 0,DP 0x00809856 0x087600f4 ldi 244,IE ; Enable XINT/RINT/INT2 0x00809857 0x08710004 ldi 4,ir0 0x00809858 0x08631000 LDI 4096,R3 0x00809859 0x0860ffff ldi -1,R0 0x0080985a 0x01e0f000 addf .5,R0 0x0080985b 0x0864ffff ldi -1,R4 0x0080985c 0xd1359617 and3 r6,*++ar7(1),r4 0x0080985c parcode || sti r5,*++ar6(ir1) 0x0080985d 0x25030303 MPYI3 R3,R3,R3 0x0080985e 0x8e5cbbc7 mpyi3 r4,r3,r0 0x0080985e parcode || subi3 *ar7,*ar3--(ir1)%,r3 0x0080985f 0xeb009f05 nop 0x00809860 0x0c800000 nop 0x00809861 0x0c800000 nop 0x00809862 0x0c800000 nop 0x00809863 0x0c800000 nop 0x00809864 0x0c800000 nop 0x00809865 0x0c800000 nop 0x00809866 0x0c800000 nop 0x00809867 0x0c800000 nop 0x00809868 0x0c800000 nop 0x00809869 0x6a00ffe1 b main ; Do it again! 0x0080986a nocode ;------------------------------- 0x0080986a 0x0f350000 DAC2 push ST ; DAC Interrupt service routine 0x0080986b 0x0f200000 push R0 ; 0x0080986c 0x0fa00000 pushf R0 ; 0x0080986d 0x0f220000 push R2 ; 0x0080986e 0x0fa20000 pushf R2 ; 0x0080986f 0x0f280000 push AR0 ; 0x00809870 0x0f290000 push AR1 ; 0x00809871 0x08299843 ldi @ADC_last,AR1 ; 0x00809872 0x08289844 ldi @FIR_coefx,AR0 ; 0x00809873 0x08339840 ldi @SIZE,BK 0x00809874 nocode 0x00809874 0x24e03120 FIR mpyf3 *AR0++,*AR1++(1)%,R0 0x00809875 0x07628000 ldf 0.0,R2 0x00809876 0x083b9840 ldi @SIZE,RC 0x00809877 0x187b0002 subi 2,RC 0x00809878 0x64809879 rptb FIR2 0x00809879 0x80103120 mpyf3 *AR0++,*AR1++(1)%,R0 0x00809879 parcode FIR2 || addf3 R0,R2,R2 0x0080987a 0x01800002 addf R2,R0 0x0080987b nocode 0x0080987b 0x05000000 fix R0,R0 0x0080987c 0x03600003 andn 3,R0 ; 0x0080987d 0x15208048 sti R0,@S0_xdata ; Output the new DAC value 0x0080987e 0x0e290000 pop AR1 ; 0x0080987f 0x0e280000 pop AR0 ; 0x00809880 0x0ea20000 popf R2 ; 0x00809881 0x0e220000 pop R2 ; 0x00809882 0x0ea00000 popf R0 ; 0x00809883 0x0e200000 pop R0 ; 0x00809884 0x0e350000 pop ST ; 0x00809885 0x78000000 reti ; 0x00809886 nocode ;------------------------------- 0x00809886 0x0f350000 ADC2 push ST ; 0x00809887 0x0f230000 push R3 ; 0x00809888 0x0fa30000 pushf R3 ; 0x00809889 0x0f280000 push AR0 ; 0x0080988a 0x0823804c ldi @S0_rdata,R3 ; 0x0080988b nocode 0x0080988b 0x09e30010 lsh 16,R3 0x0080988c 0x03e3fff0 ash -16,R3 0x0080988d nocode 0x0080988d 0x08289843 ldi @ADC_last,AR0 0x0080988e 0x05830003 float R3,R3 0x0080988f 0x14432001 stf R3,*AR0++ 0x00809890 nocode 0x00809890 0x04a89842 cmpi @ADC_end,AR0 0x00809891 0x55289841 ldige @ADC_first,AR0 0x00809892 0x15289843 sti AR0,@ADC_last 0x00809893 nocode 0x00809893 0x0e280000 pop AR0 0x00809894 0x0ea30000 popf R3 ; 0x00809895 0x0e230000 pop R3 ; 0x00809896 0x0e350000 pop ST ; 0x00809897 0x78000000 reti ; 0x00809898 nocode ;*****************************************************; 0x00809898 nocode ; The startup stub is used during initialization only ; 0x00809898 nocode ; and can be safely overwritten by the stack or data ; 0x00809898 nocode ;*****************************************************; 0x00809898 nocode ;.entry ST_STUB ; Debugger starts here 0x00809898 0x50700080 ST_STUB ldp T0_ctrl ; Use kernel data page and stack 0x00809899 0x083498c9 ldi @stack,SP 0x0080989a 0x08600000 ldi 0,R0 ; Halt TIM0 & TIM1 0x0080989b 0x15208020 sti R0,@T0_ctrl ; 0x0080989c 0x15208024 sti R0,@T0_count ; Set counts to 0 0x0080989d 0x08600001 ldi 1,R0 ; Set periods to 1 0x0080989e 0x15208028 sti R0,@T0_prd ; 0x0080989f 0x086002c1 ldi 0x2C1,R0 ; Restart both timers 0x008098a0 0x15208020 sti R0,@T0_ctrl ; 0x008098a1 nocode ;--------------------- 0x008098a1 0x08209849 ldi @S0_xctrl_val,R0; 0x008098a2 0x15208042 sti R0,@S0_xctrl ; transmit control 0x008098a3 0x0820984a ldi @S0_rctrl_val,R0; 0x008098a4 0x15208043 sti R0,@S0_rctrl ; receive control 0x008098a5 0x08600000 ldi 0,R0 ; 0x008098a6 0x15208048 sti R0,@S0_xdata ; DXR data value 0x008098a7 0x08209848 ldi @S0_gctrl_val,R0; Setup serial port 0x008098a8 0x15208040 sti R0,@S0_gctrl ; global control 0x008098a9 nocode ;======================================================; 0x008098a9 nocode ; This section of code initializes the AIC ; 0x008098a9 nocode ;======================================================; 0x008098a9 0x08760010 AIC_INIT LDI 0x10,IE ; Enable only XINT interrupt 0x008098aa 0x03770034 andn 0x34,IF ; 0x008098ab 0x08600000 ldi 0,R0 ; 0x008098ac 0x15208048 sti R0,@S0_xdata ; 0x008098ad 0x13fb0040 RPTS 0x040 ; 0x008098ae 0x08780002 LDI 2,IOF ; XF0=0 resets AIC 0x008098af 0x13fb0040 rpts 0x40 ; 0x008098b0 0x08780006 LDI 6,IOF ; XF0=1 runs AIC 0x008098b1 nocode ;--------------------- 0x008098b1 0x08209847 ldi @C_REG,R0 ; Setup control register 0x008098b2 0x628098bc call prog_AIC ; 0x008098b3 0x0860fffc ldi 0xfffc ,R0 ; Program the AIC to be real slow 0x008098b4 0x628098bc call prog_AIC ; 0x008098b5 0x0860fffe ldi 0xfffc|2,R0 ; 0x008098b6 0x628098bc call prog_AIC ; 0x008098b7 0x08209846 ldi @B_REG,R0 ; Bump up the Fs to final rate 0x008098b8 0x628098bc call prog_AIC ; (smallest divisor should be last) 0x008098b9 0x08209845 ldi @A_REG,R0 ; 0x008098ba 0x628098bc call prog_AIC ; 0x008098bb 0x6a00ff8f b main ; the DRR before going to the main loop 0x008098bc nocode ;------------------------------- 0x008098bc 0x08218048 prog_AIC ldi @S0_xdata,R1 ; Use original DXR data during 2 ndy 0x008098bd 0x15218048 sti R1,@S0_xdata ; 0x008098be 0x06000000 idle 0x008098bf 0x08218048 ldi @S0_xdata,R1 ; Use original DXR data during 2 ndy 0x008098c0 0x10610003 or 3,R1 ; Request 2 ndy XMIT 0x008098c1 0x15218048 sti R1,@S0_xdata ; 0x008098c2 0x06000000 idle ; 0x008098c3 0x15208048 sti R0,@S0_xdata ; Send register value 0x008098c4 0x06000000 idle ; 0x008098c5 0x03610003 andn 3,R1 ; 0x008098c6 0x15218048 sti R1,@S0_xdata ; Leave with original safe value in DXR 0x008098c7 nocode ;--------------------- 0x008098c7 0x0820804c ldi @S0_rdata,R0 ; Fix the receiver underrun by reading 0x008098c8 0x78800000 rets ; 0x008098c9 directive stack .word $ ; Put stack here 0x008098c9 0x008098c9 0x008098ca nocode ;****************************************************; 0x008098ca nocode ; Install the XINT/RINT ISR handler directly into ; 0x008098ca nocode ; the vector RAM location it will be used for ; 0x008098ca nocode ;****************************************************; 0x008098ca directive .start "SP0VECTS",0x809FC5 0x008098ca directive .sect "SP0VECTS" 0x00809fc5 0x6a00f8a4 B DAC2 ; XINT0 0x00809fc6 0x6a00f8bf B ADC2 ; RINT0 >>>> >>>> PASS 2 Complete >>>> Errors: 0 Warnings: 0 >>>> >>>> ENTRY 0x0080984b >>>> >>>> Symbol reference table Type Addressable >>>> ref Default_sect 0x00809802 1 1 >>>> ref TA 0x00000008 1 0 >>>> ref TB 0x00000010 1 0 >>>> ref RA 0x00000008 1 0 >>>> ref RB 0x00000010 1 0 >>>> ref GIE 0x00002000 1 0 >>>> ref DMA_ctrl 0x00808000 1 0 >>>> ref DMA_srce 0x00808004 1 0 >>>> ref DMA_dest 0x00808006 1 0 >>>> ref DMA_xfr 0x00808008 1 0 >>>> ref T0_ctrl 0x00808020 1 0 >>>> ref T0_count 0x00808024 1 0 >>>> ref T0_prd 0x00808028 1 0 >>>> ref T1_ctrl 0x00808030 1 0 >>>> ref T1_count 0x00808034 1 0 >>>> ref T1_prd 0x00808038 1 0 >>>> ref S0_gctrl 0x00808040 1 0 >>>> ref S0_xctrl 0x00808042 1 0 >>>> ref S0_rctrl 0x00808043 1 0 >>>> ref S0_tctrl 0x00808044 1 0 >>>> ref S0_tcount 0x00808045 1 0 >>>> ref S0_tprd 0x00808046 1 0 >>>> ref S0_xdata 0x00808048 1 0 >>>> ref S0_rdata 0x0080804c 1 0 >>>> ref S1_gctrl 0x00808050 1 0 >>>> ref S1_xctrl 0x00808052 1 0 >>>> ref S1_rctrl 0x00808053 1 0 >>>> ref S1_tctrl 0x00808054 1 0 >>>> ref S1_tcount 0x00808055 1 0 >>>> ref S1_tprd 0x00808056 1 0 >>>> ref S1_xdata 0x00808058 1 0 >>>> ref S1_rdata 0x0080805c 1 0 >>>> ref e_buscon 0x00808060 1 0 >>>> ref p_buscon 0x00808064 1 0 >>>> ref JJUMP 0x00809ff4 1 0 >>>> ref JXWRIT 0x00809ff5 1 0 >>>> ref JXREAD 0x00809ff6 1 0 >>>> ref JXCTXT 0x00809ff7 1 0 >>>> ref JXRUNF 0x00809ff8 1 0 >>>> ref JXSTEP 0x00809ff9 1 0 >>>> ref JXHALT 0x00809ffa 1 0 >>>> ref JW_HOST 0x00809ffb 1 0 >>>> ref JR_HOST 0x00809ffc 1 0 >>>> ref JSPARE 0x00809ffd 1 0 >>>> ref AICTEST 0x00809820 1 1 >>>> ref ADC_recv 0x00809820 2 1 >>>> ref FIR_coef 0x00809830 2 1 >>>> ref END_coef 0x00809840 1 1 >>>> ref BufSz 0x00000010 1 0 >>>> ref SIZE 0x00809840 1 1 >>>> ref ADC_first 0x00809841 1 1 >>>> ref ADC_end 0x00809842 1 1 >>>> ref ADC_last 0x00809843 1 1 >>>> ref FIR_coefx 0x00809844 1 1 >>>> ref A_REG 0x00809845 1 1 >>>> ref B_REG 0x00809846 1 1 >>>> ref C_REG 0x00809847 1 1 >>>> ref S0_gctrl_val 0x00809848 1 1 >>>> ref S0_xctrl_val 0x00809849 1 1 >>>> ref S0_rctrl_val 0x0080984a 1 1 >>>> ref main 0x0080984b 1 1 >>>> ref DAC2 0x0080986a 1 1 >>>> ref FIR 0x00809874 1 1 >>>> ref FIR2 0x00809879 1 1 >>>> ref ADC2 0x00809886 1 1 >>>> ref ST_STUB 0x00809898 1 1 >>>> ref AIC_INIT 0x008098a9 1 1 >>>> ref prog_AIC 0x008098bc 1 1 >>>> ref stack 0x008098c9 1 1 >>>> ref SP0VECTS 0x00809fc5 1 1 >>>> >>>> Output section start end length >>>> sect Default_sect 0x00809802 0x00809802 0x00000000 >>>> sect AICTEST 0x00809820 0x008098ca 0x000000aa >>>> sect SP0VECTS 0x00809fc5 0x00809fc7 0x00000002 >>>> >>>> >>>> END DSK