>>>> DSK3A C3x DSP Starter Kit Assembler Rev 1.17 >>>> (c) Copyright 1994-1995 Texas Instruments Incorporated >>>> Mon Oct 27 15:22:58 1997 >>>> DSKSG.ASM >>>> >>>> Include Open : C3XMMRS.ASM >>>> Include Close: C3XMMRS.ASM >>>> >>>> PASS 1 Complete >>>> Errors: 0 Warnings: 0 >>>> 0x00809802 nocode ;--------------------------------------------------------------- 0x00809802 nocode ; DSKSG.ASM 0x00809802 nocode ; Keith Larson 0x00809802 nocode ; TMS320 DSP Applications 0x00809802 nocode ; (C) Copyright 1995,1996 0x00809802 nocode ; Texas Instruments Incorporated 0x00809802 nocode ; 0x00809802 nocode ; This is unsupported freeware with no implied warranties or 0x00809802 nocode ; liabilities. See the disclaimer document for details 0x00809802 nocode ;---------------------------------------------------------------- 0x00809802 nocode ; DSKSG.ASM is a precision signal generator application which uses 0x00809802 nocode ; a wave table lookup to create multiple precision signals. The 0x00809802 nocode ; table lookup scheme uses both interpolation in time and level to 0x00809802 nocode ; achieve precision in frequency and in level 0x00809802 nocode ; 0x00809802 nocode ; NOTE: Please see DSKDTMF.ASM for generating ultra-precise 'pure' 0x00809802 nocode ; sine waves. This application will even produce both the 0x00809802 nocode ; sine and cosine (complex conjugate) at the same time. 0x00809802 nocode ; 0x00809802 nocode ; Sine Generation 0x00809802 nocode ; --------------- 0x00809802 nocode ; DSKSG.ASM generates a sine wave when the SINE_SG.ASM file has been 0x00809802 nocode ; assembled and loaded into the signal lookup table. 0x00809802 nocode ; 0x00809802 nocode ; The output waveform is produced by assuming that the table length 0x00809802 nocode ; of N=128 samples is 2*PI radians. The desired frequency (radian 0x00809802 nocode ; accumulation rate) is then used to determine both the whole step 0x00809802 nocode ; step values and also a residual step which is used in a first order 0x00809802 nocode ; interpolation (slope and intercept). 0x00809802 nocode ; 0x00809802 nocode ; NOTE: This technique produces 32 bit floating point frequency accuracy 0x00809802 nocode ; with excellent amplitude precision for signals that fit the 0x00809802 nocode ; interpolation and sampling criteria. For a sine wave, linear 0x00809802 nocode ; interpolation will result in approximately 2x the bits of precision 0x00809802 nocode ; used in the lookup, or about 14 bits in a 7 bit (128 element) table. 0x00809802 nocode ; 0x00809802 nocode ; The output amplitude of each signal wave is then controlled by a scale 0x00809802 nocode ; factor. 0x00809802 nocode ;--------------------------------------------------------------- 0x00809802 directive TA .set 11 ; AIC Default startup matches host side app 0x00809802 directive TB .set 18 ; 0x00809802 directive RA .set 11 ; 0x00809802 directive RB .set 18 ; 0x00809802 directive .include "C3XMMRS.ASM" 0x00809802 nocode ;-------------------------------------------------------------------- 0x00809802 nocode ; C3XMMRS.ASM 0x00809802 nocode ; Keith Larson 0x00809802 nocode ; TMS320 DSP Applications 0x00809802 nocode ; (C) Copyright 1995,1996 0x00809802 nocode ; Texas Instruments Incorporated 0x00809802 nocode ; 0x00809802 nocode ; This is unsupported freeware with no implied warranties or 0x00809802 nocode ; liabilities. See the disclaimer document for details 0x00809802 nocode ; 0x00809802 nocode ; MMR address locations for the TMS320C30 and TMS320C31 0x00809802 nocode ; 0x00809802 nocode ; Use a .include "C3XMMRS.ASM" within your application code 0x00809802 nocode ; to define the locations of the following locations 0x00809802 nocode ;-------------------------------------------------------------------- 0x00809802 directive DMA_ctrl .set 0x808000; DMA cntl 0x00809802 directive DMA_srce .set 0x808004; DMA srce address 0x00809802 directive DMA_dest .set 0x808006; DMA dest address 0x00809802 directive DMA_xfr .set 0x808008; DMA xfer counter 0x00809802 directive T0_ctrl .set 0x808020; TIM0 gl control 0x00809802 directive T0_count .set 0x808024; TIM0 count 0x00809802 directive T0_prd .set 0x808028; TIM0 prd 0x00809802 directive T1_ctrl .set 0x808030; TIM1 gl control 0x00809802 directive T1_count .set 0x808034; TIM1 count 0x00809802 directive T1_prd .set 0x808038; TIM1 prd 0x00809802 directive S0_gctrl .set 0x808040; SP 0 global control 0x00809802 directive S0_xctrl .set 0x808042; SP 0 FSX/DX/CLKX port ctl 0x00809802 directive S0_rctrl .set 0x808043; SP 0 FSR/DR/CLKR port ctl 0x00809802 directive S0_tctrl .set 0x808044; SP 0 R/X timer control 0x00809802 directive S0_tcount .set 0x808045; SP 0 R/X timer counter 0x00809802 directive S0_tprd .set 0x808046; SP 0 R/X timer period 0x00809802 directive S0_xdata .set 0x808048; SP 0 Data transmit 0x00809802 directive S0_rdata .set 0x80804C; SP 0 Data receive 0x00809802 directive S1_gctrl .set 0x808050; SP 1 global control 0x00809802 directive S1_xctrl .set 0x808052; SP 1 FSX/DX/CLKX port ctl 0x00809802 directive S1_rctrl .set 0x808053; SP 1 FSR/DR/CLKR port ctl 0x00809802 directive S1_tctrl .set 0x808054; SP 1 R/X timer control 0x00809802 directive S1_tcount .set 0x808055; SP 1 R/X timer counter 0x00809802 directive S1_tprd .set 0x808056; SP 1 R/X timer period 0x00809802 directive S1_xdata .set 0x808058; SP 1 Data transmit 0x00809802 directive S1_rdata .set 0x80805C; SP 1 Data receive 0x00809802 directive e_buscon .set 0x808060; Exp bus control 0x00809802 directive p_buscon .set 0x808064; Pri bus control 0x00809802 nocode ; 0x00809802 nocode ; Kernel functions can be accessed through the function 0x00809802 nocode ; jump table which holds the address of each function 0x00809802 nocode ; 0x00809802 directive JJUMP .set 0x809ff4 ;<- Base address 0x00809802 directive JXWRIT .set 0x809ff5 ; 0x00809802 directive JXREAD .set 0x809ff6 ; 0x00809802 directive JXCTXT .set 0x809ff7 ; 0x00809802 directive JXRUNF .set 0x809ff8 ; 0x00809802 directive JXSTEP .set 0x809ff9 ; 0x00809802 directive JXHALT .set 0x809ffA ; 0x00809802 directive JW_HOST .set 0x809ffB ; 0x00809802 directive JR_HOST .set 0x809ffC ; 0x00809802 directive JSPARE .set 0x809ffd ; 0x00809802 nocode ;================================================== 0x00809802 nocode ; Create a bit-reversed (circular addressable) sinewave lookup table 0x00809802 nocode ;================================================== 0x00809802 directive .start "TABLE",0X809800 0x00809802 directive .sect "TABLE" 0x00809800 directive N .set 128 0x00809800 nocode ;================================================== 0x00809800 directive .start "CODE",0x809C00 ; Start of RAM1 0x00809800 directive .sect "CODE" ; 0x00809c00 nocode ;================================================== 0x00809c00 directive _STOP .set 1 0x00809c00 directive _START .set 2 0x00809c00 nocode ; 0x00809c00 directive MSG_BOX .word 0 ; 0x809C00 0x00809c00 0x00000000 0x00809c01 directive A_REG .word (TA<<9)+(RA<<2)+0 ; 0x809C01 0x00809c01 0x0000162c 0x00809c02 directive B_REG .word (TB<<9)+(RB<<2)+2 ; 0x809C02 0x00809c02 0x0000244a 0x00809c03 directive C_REG .word 00000011b ; 0x809C03 +/- 1.5 V 0x00809c03 0x00000003 0x00809c04 directive LOAD .word 1 ; 0x809C04 set to 1 to reload AIC 0x00809c04 0x00000001 0x00809c05 nocode 0x00809c05 directive .word 0 ; 0x809C05 NOISE ON/OFF 0x00809c05 0x00000000 0x00809c06 directive WNOISELVL .float 1.0 ; 0x809C06 0x00809c06 0x00000000 0x00809c07 directive WNOISESCL .word -18<<24 ; 0x809C07 <- NOT MODIFIED BY HOST 0x00809c07 0xee000000 0x00809c08 directive OFF_LVL .float 0.0 ; 0x809C08 0x00809c08 0x80000000 0x00809c09 nocode 0x00809c09 directive MAXTBL .set 16 ; Maximum entries in table 0x00809c09 nocode PHASEx 0x00809c09 directive .loop MAXTBL 0x00809c09 0x80000000 0x00809c0a 0x80000000 0x00809c0b 0x80000000 0x00809c0c 0x80000000 0x00809c0d 0x80000000 0x00809c0e 0x80000000 0x00809c0f 0x80000000 0x00809c10 0x80000000 0x00809c11 0x80000000 0x00809c12 0x80000000 0x00809c13 0x80000000 0x00809c14 0x80000000 0x00809c15 0x80000000 0x00809c16 0x80000000 0x00809c17 0x80000000 0x00809c18 0x80000000 0x00809c19 0x80000000 0x00809c1a 0x80000000 0x00809c1b 0x80000000 0x00809c1c 0x80000000 0x00809c1d 0x80000000 0x00809c1e 0x80000000 0x00809c1f 0x80000000 0x00809c20 0x80000000 0x00809c21 0x80000000 0x00809c22 0x80000000 0x00809c23 0x80000000 0x00809c24 0x80000000 0x00809c25 0x80000000 0x00809c26 0x80000000 0x00809c27 0x80000000 0x00809c28 0x80000000 0x00809c29 0x80000000 0x00809c2a 0x80000000 0x00809c2b 0x80000000 0x00809c2c 0x80000000 0x00809c2d 0x80000000 0x00809c2e 0x80000000 0x00809c2f 0x80000000 0x00809c30 0x80000000 0x00809c31 0x80000000 0x00809c32 0x80000000 0x00809c33 0x80000000 0x00809c34 0x80000000 0x00809c35 0x80000000 0x00809c36 directive .float 0 ; 0x809C09 Phase accumulation rate 0x00809c36 0x80000000 0x00809c37 directive .float 0 ; 0x809C0A Current offset into array 0x00809c37 0x80000000 0x00809c38 directive .float 0 ; 0x809C0B Amplitude of term 0x00809c38 0x80000000 0x00809c39 directive .endloop 0x00809c39 directive .float 0.0 ; Terminate table 0x00809c39 0x80000000 0x00809c3a nocode ;-------------------------------- 0x00809c3a directive FTBL .word PHASEx 0x00809c3a 0x00809c09 0x00809c3b nocode 0x00809c3b directive First_Add .word TABLE ; 0x00809c3b 0x00809800 0x00809c3c directive Last_Add .word TABLE+N ; 0x00809c3c 0x00809880 0x00809c3d directive FLAGS .word 0 ; 0x00809c3d 0x00000000 0x00809c3e directive NF .float N ; 0x00809c3e 0x07000000 0x00809c3f nocode ; 0x00809c3f directive S0_gctrl_val .word 0x0E970300 ; Runtime value XINT/RINT enabled 0x00809c3f 0x0e970300 0x00809c40 directive S0_xctrl_val .word 0x00000111 ; 0x00809c40 0x00000111 0x00809c41 directive S0_rctrl_val .word 0x00000111 ; 0x00809c41 0x00000111 0x00809c42 nocode ; 0x00809c42 directive PHASE .set 0 0x00809c42 directive OFFS .set 1 0x00809c42 directive A_LVL .set 2 0x00809c42 nocode ;------------------------------- 0x00809c42 0x08760034 main ldi 0x34,IE ; 0x00809c43 0x06000000 idle ; Wait for next ADC sample 0x00809c44 nocode ;- - - - - - - - - - - 0x00809c44 0x08229c04 ldi @LOAD,R2 ; If signalled by host, reinitialize AIC 0x00809c45 0x6a05fffc bz main ; 0x00809c46 0x62809cce call AIC_INIT ; Restart with new AIC setup 0x00809c47 nocode 0x00809c47 0x03752000 andn GIE,ST 0x00809c48 0x087b000f ldi MAXTBL-1,RC 0x00809c49 0x08289c3a ldi @FTBL,AR0 0x00809c4a 0x08620000 ldi 0,R2 0x00809c4b 0x64809c4d rptb INITBL 0x00809c4c 0x15420001 sti R2,*+AR0(OFFS) 0x00809c4d 0x0cc01003 INITBL nop *++AR0(3) 0x00809c4e nocode 0x00809c4e 0x08620000 ldi 0,R2 ; reset the LOAD flag 0x00809c4f 0x15229c04 sti R2,@LOAD ; 0x00809c50 0x6a00fff1 b main ; close loop 0x00809c51 nocode ;============================================================================= 0x00809c51 directive MinS .float -16000.0 0x00809c51 0x0d860000 0x00809c52 directive MaxS .float 16000.0 0x00809c52 0x0d7a0000 0x00809c53 nocode 0x00809c53 directive RACC .set 0 0x00809c53 directive IACC .set 1 0x00809c53 directive RSIG .set 2 0x00809c53 directive ISIG .set 3 0x00809c53 directive MAGN .set 4 0x00809c53 directive pi .set 3.14159265 0x00809c53 directive Rpi .set 2.0*pi/360.0 0x00809c53 nocode 0x00809c53 directive SFFTdata .word $+1 0x00809c53 0x00809c54 0x00809c54 directive .float cos(Rpi*40.0) ; phase accumulation rate 0x00809c54 0xff441b7d 0x00809c55 directive .float sin(Rpi*40.0) ; 10' per step 0x00809c55 0xff248dbb 0x00809c56 directive .float 1.0 ; vector length is unity at all times 0x00809c56 0x00000000 0x00809c57 directive .float 0.0 ; and rotates at phase accumulation rate 0x00809c57 0x80000000 0x00809c58 directive .float 0.5 ; 0x00809c58 0xff000000 0x00809c59 nocode 0x00809c59 directive .float cos(Rpi*41.01) ; 0x00809c59 0xff412d25 0x00809c5a directive .float sin(Rpi*41.01) ; 0x00809c5a 0xff27fc1d 0x00809c5b directive .float 1.0 ; 0x00809c5b 0x00000000 0x00809c5c directive .float 0.0 ; 0x00809c5c 0x80000000 0x00809c5d directive .float 0.5 ; 0x00809c5d 0xff000000 0x00809c5e nocode 0x00809c5e directive .float 0.0 0x00809c5e 0x80000000 0x00809c5f nocode 0x00809c5f directive FX .float 0 0x00809c5f 0x80000000 0x00809c60 0x0f350000 ADC push ST ; On interrupt, set a software flag to 0x00809c61 0x0f200000 push R0 ; let the CPU know that the RINT has been 0x00809c62 0x0820804c ldi @S0_rdata,R0 ; received 0x00809c63 0x08209c3d ldi @FLAGS,R0 ; 0x00809c64 0x10600020 or 0x20,R0 ; 0x00809c65 0x15209c3d sti R0,@FLAGS ; 0x00809c66 0x0e200000 pop R0 ; 0x00809c67 0x0e350000 pop ST ; 0x00809c68 0x78000000 reti ; 0x00809c69 nocode ;- - - - - - - - - - - 0x00809c69 0x0f350000 DAC push ST ; 0x00809c6a 0x0f200000 push R0 ; 0x00809c6b 0x0fa00000 pushf R0 ; 0x00809c6c 0x0f210000 push R1 ; 0x00809c6d 0x0fa10000 pushf R1 ; 0x00809c6e 0x0f220000 push R2 ; 0x00809c6f 0x0fa20000 pushf R2 ; 0x00809c70 0x0f230000 push R3 ; 0x00809c71 0x0fa30000 pushf R3 ; 0x00809c72 0x0f240000 push R4 ; 0x00809c73 0x0fa40000 pushf R4 ; 0x00809c74 nocode 0x00809c74 0x0f290000 push AR1 0x00809c75 0x0f320000 push IR1 ; 0x00809c76 nocode ;======================================================================= 0x00809c76 0x07618000 ldf 0,R1 ; 0x00809c77 0x08299c3a ldi @FTBL,AR1 ; Load start of F,A pairs 0x00809c78 0x14219c5f stf R1,@FX ; 0x00809c79 nocode ;======================; Calculate F,A pairs 0x00809c79 0x07410101 NextPair ldf *+AR1(OFFS),R1 ; Accumulate phase 0x00809c7a 0x01c10100 addf *+AR1(PHASE),R1 ; 2*PI radians of phase offset == N samples 0x00809c7b 0x04219c3e cmpf @NF,R1 ; Check for phase offset rollover 0x00809c7c 0x6a070001 blt Bypass ; 0x00809c7d 0x17a19c3e subf @NF,R1 ; 0x00809c7e 0x14410101 Bypass stf R1,*+AR1(OFFS) ; Save the new phase offset 0x00809c7f 0x07020001 ldf R1,R2 ; R2>= R1 0x00809c80 0x05010001 fix R1,R1 ; R1 = offset is now 0-N integer 0x00809c81 0x05810001 float R1,R1 ; 0x00809c82 0x17820001 subf R1,R2 ; R2 = 0.000->0.999 fraction of step 0x00809c83 0x05010001 fix R1,R1 ; 0x00809c84 0x08289c3b ldi @First_Add,AR0 ; 0x00809c85 0x02080001 addi R1,AR0 ; 0x00809c86 0x07412001 ldf *AR0++,R1 ; Get 1 st data point, point to next 0x00809c87 0x03680080 andn N,AR0 ; Circular roll for 2^N tables on 2^N boundary 0x00809c88 nocode ;- - - - - - - - - - - 0x00809c88 0x07000001 ldf R1,R0 ; Linear Interpolation doubles mantissa 0x00809c89 0x1940c000 subrf *AR0,R0 ; bit accuracy (7 bits to 14 bits) 0x00809c8a 0x0a020000 mpyf R0,R2 ; 0x00809c8b 0x01810002 addf R2,R1 ; accuracy is now improved 0x00809c8c 0x0a410102 mpyf *+AR1(A_LVL),R1 ; Magnitude scaling 0x00809c8d nocode ;===================== 0x00809c8d 0x01a19c5f addf @FX,R1 ; Sum results 0x00809c8e 0x14219c5f stf R1,@FX ; Save sum 0x00809c8f 0x02690003 addi 3,AR1 ; point to next pair 0x00809c90 0x07410100 ldf *+AR1(PHASE),R1 ; is this the end (phase accum=0)? 0x00809c91 0x6a06ffe7 bnz NextPair ; 0x00809c92 nocode ;======================================================================= 0x00809c92 0x07219c5f ldf @FX,R1 ; Reload sum of pairs 0x00809c93 0x01a19c08 addf @OFF_LVL ,R1 ; Offset addition 0x00809c94 nocode ;--------------------- 0x00809c94 0x07209c06 ldf @WNOISELVL,R0 ; If white noise level != 0.0 0x00809c95 0x72060017 ADD_NOISE callnz RANDX ; Get next 32 bit random 0x00809c96 0x05800000 float R0,R0 ; convert to float 0x00809c97 0x0a209c07 mpyf @WNOISESCL,R0 ; scale to +/-1.0 0x00809c98 0x0a209c06 mpyf @WNOISELVL,R0 ; 0x00809c99 0x01810000 addf R0,R1 ; 0x00809c9a nocode ;--------------------- 0x00809c9a 0x0a219cb5 NO_NOISE mpyf @SATURATE,R1 ; Using the ALU saturation mode saves 2 0x00809c9b 0x0a219cb6 mpyf @UNSATUR8,R1 ; cycles compared to magnitude comparison 0x00809c9c 0x05010001 fix R1,R1 ; Convert to fixed point 0x00809c9d 0x03610003 andn 3,R1 ; Clear MSBs to prevent AIC reprogramming 0x00809c9e 0x15218048 sti R1,@S0_xdata ; output the DAC value 0x00809c9f nocode ;- - - - - - - - - - - 0x00809c9f 0x0e320000 pop IR1 ; Restore register context before return 0x00809ca0 0x0e290000 pop AR1 0x00809ca1 0x0ea40000 popf R4 ; 0x00809ca2 0x0e240000 pop R4 ; 0x00809ca3 0x0ea30000 popf R3 ; 0x00809ca4 0x0e230000 pop R3 ; 0x00809ca5 0x0ea20000 popf R2 ; 0x00809ca6 0x0e220000 pop R2 ; 0x00809ca7 0x0ea10000 popf R1 ; 0x00809ca8 0x0e210000 pop R1 ; 0x00809ca9 0x0ea00000 popf R0 ; 0x00809caa 0x0e200000 pop R0 ; 0x00809cab 0x0e350000 pop ST ; 0x00809cac 0x78000000 reti ; return from interrupt 0x00809cad nocode ;---------------------------------------- 0x00809cad nocode ; Fast 32 bit random number generator 0x00809cad nocode ;---------------------------------------- 0x00809cad 0x08209cb4 RANDX: ldi @SEED,R0 ; Call here for last SEED 0x00809cae 0x0aa09cb2 RAND: mpyi @A,R0 ; Calculate RAND(R0) 0x00809caf 0x02209cb3 addi @C,R0 ; 0x00809cb0 0x15209cb4 sti R0,@SEED ; Result is returned in R0 0x00809cb1 0x78800000 rets ; 0x00809cb2 nocode ;---------------------- 0x00809cb2 directive A .word 0107465h ; Constants needed for RAND 0x00809cb2 0x00107465 0x00809cb3 directive C .word 0234567h ; 0x00809cb3 0x00234567 0x00809cb4 directive SEED .word 0 ; 0x00809cb4 0x00000000 0x00809cb5 nocode ;- - - - - - - - - - - - - - - - 0x00809cb5 nocode ; By using the saturation feature of the 0x00809cb5 nocode ; TMS320C3x ALU during multiplies, several 0x00809cb5 nocode ; cycles can be shaved off of a compare/load 0x00809cb5 nocode ; clipping operation 0x00809cb5 nocode ; 0x00809cb5 directive SATURATE .word 113<<24 ; Since max AIC magnitude is 2^15, multiply 0x00809cb5 0x71000000 0x00809cb6 directive UNSATUR8 .word -113<<24 ; by 2^113 which results in 2^128. The 0x00809cb6 0x8f000000 0x00809cb7 nocode ; multiplier constant is created by directly 0x00809cb7 nocode ; placing the value of 113 into the exponent 0x00809cb7 nocode ; exponent field of a 32 bit hex number. 0x00809cb7 nocode ;-------------------------------- 0x00809cb7 directive GIE .set 0x2000 0x00809cb7 nocode 0x00809cb7 nocode myidle ; idle 0x00809cb7 nocode ; rets 0x00809cb7 nocode 0x00809cb7 0x03752000 andn GIE,ST ; Use XINT polling during setup to 0x00809cb8 0x1a770010 tstb 0x10,IF ; avoid contaminating the DXR during 0x00809cb9 0x6a05fffe bz $-1 ; programming 0x00809cba 0x03770010 andn 0x10,IF ; 0x00809cbb nocode ;idle ; 0x00809cbb 0x78800000 rets ; 0x00809cbc nocode 0x00809cbc 0x0f210000 prog_AIC push R1 ; 0x00809cbd 0x0f360000 push IE ; 0x00809cbe 0x08760010 ldi 0x10,IE ; 0x00809cbf 0x03770030 andn 0x30,IF ; 0x00809cc0 0x08218048 ldi @S0_xdata,R1 ; Use original DXR data during 2 ndy 0x00809cc1 0x15218048 sti R1,@S0_xdata ; 0x00809cc2 0x62809cb7 call myidle 0x00809cc3 0x08218048 ldi @S0_xdata,R1 ; Use original DXR data during 2 ndy 0x00809cc4 0x10610003 or 3,R1 ; Request 2 ndy XMIT 0x00809cc5 0x15218048 sti R1,@S0_xdata ; 0x00809cc6 0x62809cb7 call myidle ; 0x00809cc7 0x15208048 sti R0,@S0_xdata ; Send register value 0x00809cc8 0x62809cb7 call myidle ; 0x00809cc9 nocode ; andn 3,R1 ; 0x00809cc9 0x08610000 ldi 0,R1 0x00809cca 0x15218048 sti R1,@S0_xdata ; Leave with original safe value in DXR 0x00809ccb 0x0e360000 pop IE ; 0x00809ccc 0x0e210000 pop R1 ; 0x00809ccd 0x78800000 rets ; 0x00809cce nocode ;======================================================; 0x00809cce nocode ; This section of code is called by the initialization ; 0x00809cce nocode ; code as well as by the main program loop. It is ; 0x00809cce nocode ; therfor assembled into the regular program RAM ; 0x00809cce nocode ;======================================================; 0x00809cce 0x0f200000 AIC_INIT push R0 ; 0x00809ccf 0x08760010 LDI 0x10,IE ; Enable XINT interrupt 0x00809cd0 0x03770034 andn 0x34,IF ; 0x00809cd1 nocode AIC_reset 0x00809cd1 0x08780002 LDI 2,IOF ; XF0=0 resets AIC 0x00809cd2 0x08600000 ldi 0,R0 ; 0x00809cd3 0x13fb0040 rpts 0x40 ; 0x00809cd4 0x15208048 sti R0,@S0_xdata ; 0x00809cd5 nocode 0x00809cd5 0x08780006 LDI 6,IOF ; XF0=1 runs AIC 0x00809cd6 0x08600000 ldi 0,R0 ; 0x00809cd7 0x13fb0040 rpts 0x40 ; 0x00809cd8 0x15208048 sti R0,@S0_xdata ; 0x00809cd9 0x0820804c ldi @S0_rdata,R0 ; 0x00809cda nocode ;----------------------------- 0x00809cda 0x08209c03 ldi @C_REG,R0 ; Setup control register 0x00809cdb 0x62809cbc call prog_AIC ; 0x00809cdc 0x0860fffc ldi 0xfffc ,R0 ; Program the AIC to be real slow 0x00809cdd 0x62809cbc call prog_AIC ; 0x00809cde 0x0860fffe ldi 0xfffc|2,R0 ; 0x00809cdf 0x62809cbc call prog_AIC ; 0x00809ce0 0x08209c02 ldi @B_REG,R0 ; Bump up the Fs to final rate 0x00809ce1 0x62809cbc call prog_AIC ; (smallest divisor should be last) 0x00809ce2 0x08209c01 ldi @A_REG,R0 ; 0x00809ce3 0x62809cbc call prog_AIC ; 0x00809ce4 0x0e200000 pop R0 ; 0x00809ce5 0x08600000 ldi 0,R0 ; Put a safe 0 in DXR 0x00809ce6 0x15208048 sti R0,@S0_xdata ; 0x00809ce7 0x0820804c ldi @S0_rdata,R0 ; Clear receive underrun 0x00809ce8 0x78800000 rets ; 0x00809ce9 nocode ;*****************************************************; 0x00809ce9 nocode ; Startup stub... ; 0x00809ce9 nocode ; ; 0x00809ce9 nocode ; The following section of code is used only once for ; 0x00809ce9 nocode ; initialization and can be safely overwritten by ; 0x00809ce9 nocode ; assembling it into the stack or volatile data ; 0x00809ce9 nocode ; storage. ; 0x00809ce9 nocode ;*****************************************************; 0x00809ce9 directive .entry ST_STUB 0x00809ce9 nocode 0x00809ce9 0x50700080 ST_STUB ldp T0_ctrl ; Use kernel data page and stack 0x00809cea 0x08349d02 ldi @stack,SP 0x00809ceb 0x08600000 ldi 0,R0 ; Halt TIM0 & TIM1 0x00809cec 0x15208020 sti R0,@T0_ctrl ; 0x00809ced 0x15208030 sti R0,@T1_ctrl ; 0x00809cee 0x15208024 sti R0,@T0_count ; Set counts to 0 0x00809cef 0x15208034 sti R0,@T1_count ; 0x00809cf0 0x08600001 ldi 1,R0 ; Set periods to 1 0x00809cf1 0x15208028 sti R0,@T0_prd ; 0x00809cf2 0x15208038 sti R0,@T1_prd ; 0x00809cf3 0x086002c1 ldi 0x2C1,R0 ; Restart both timers 0x00809cf4 0x15208020 sti R0,@T0_ctrl ; 0x00809cf5 0x15208030 sti R0,@T1_ctrl ; 0x00809cf6 nocode ;--------------------- 0x00809cf6 0x08209c40 ldi @S0_xctrl_val,R0; 0x00809cf7 0x15208042 sti R0,@S0_xctrl ; transmit control 0x00809cf8 0x08209c41 ldi @S0_rctrl_val,R0; 0x00809cf9 0x15208043 sti R0,@S0_rctrl ; receive control 0x00809cfa 0x08600000 ldi 0,R0 ; 0x00809cfb 0x15208048 sti R0,@S0_xdata ; DXR data value 0x00809cfc 0x08209c3f ldi @S0_gctrl_val,R0; Setup serial port 0x00809cfd 0x15208040 sti R0,@S0_gctrl ; global control 0x00809cfe nocode ;--------------------- 0x00809cfe 0x03770030 andn 0x30,IF 0x00809cff 0x08760030 ldi 0x30,IE ; Service both RINT/XINT 0x00809d00 nocode 0x00809d00 nocode ; call AIC_INIT ; Initialize the AIC 0x00809d00 nocode 0x00809d00 0x0820804c ldi @S0_rdata,R0 ; 0x00809d01 0x6a00ff40 b main ; 0x00809d02 directive stack .word $+1 0x00809d02 0x00809d03 0x00809d03 nocode ;****************************************************; 0x00809d03 nocode ; Install the XINT/RINT ISR handler directly into ; 0x00809d03 nocode ; the vector RAM location it will be used in ; 0x00809d03 nocode ;****************************************************; 0x00809d03 directive .start "SP0VECTS",0x809FC5 0x00809d03 directive .sect "SP0VECTS" 0x00809fc5 0x6a00fca3 B DAC ; XINT0 0x00809fc6 0x6a00fc99 B ADC ; RINT0 >>>> >>>> PASS 2 Complete >>>> Errors: 0 Warnings: 0 >>>> >>>> ENTRY 0x00809ce9 >>>> >>>> Symbol reference table Type Addressable >>>> ref Default_sect 0x00809802 1 1 >>>> ref TA 0x0000000b 1 0 >>>> ref TB 0x00000012 1 0 >>>> ref RA 0x0000000b 1 0 >>>> ref RB 0x00000012 1 0 >>>> ref DMA_ctrl 0x00808000 1 0 >>>> ref DMA_srce 0x00808004 1 0 >>>> ref DMA_dest 0x00808006 1 0 >>>> ref DMA_xfr 0x00808008 1 0 >>>> ref T0_ctrl 0x00808020 1 0 >>>> ref T0_count 0x00808024 1 0 >>>> ref T0_prd 0x00808028 1 0 >>>> ref T1_ctrl 0x00808030 1 0 >>>> ref T1_count 0x00808034 1 0 >>>> ref T1_prd 0x00808038 1 0 >>>> ref S0_gctrl 0x00808040 1 0 >>>> ref S0_xctrl 0x00808042 1 0 >>>> ref S0_rctrl 0x00808043 1 0 >>>> ref S0_tctrl 0x00808044 1 0 >>>> ref S0_tcount 0x00808045 1 0 >>>> ref S0_tprd 0x00808046 1 0 >>>> ref S0_xdata 0x00808048 1 0 >>>> ref S0_rdata 0x0080804c 1 0 >>>> ref S1_gctrl 0x00808050 1 0 >>>> ref S1_xctrl 0x00808052 1 0 >>>> ref S1_rctrl 0x00808053 1 0 >>>> ref S1_tctrl 0x00808054 1 0 >>>> ref S1_tcount 0x00808055 1 0 >>>> ref S1_tprd 0x00808056 1 0 >>>> ref S1_xdata 0x00808058 1 0 >>>> ref S1_rdata 0x0080805c 1 0 >>>> ref e_buscon 0x00808060 1 0 >>>> ref p_buscon 0x00808064 1 0 >>>> ref JJUMP 0x00809ff4 1 0 >>>> ref JXWRIT 0x00809ff5 1 0 >>>> ref JXREAD 0x00809ff6 1 0 >>>> ref JXCTXT 0x00809ff7 1 0 >>>> ref JXRUNF 0x00809ff8 1 0 >>>> ref JXSTEP 0x00809ff9 1 0 >>>> ref JXHALT 0x00809ffa 1 0 >>>> ref JW_HOST 0x00809ffb 1 0 >>>> ref JR_HOST 0x00809ffc 1 0 >>>> ref JSPARE 0x00809ffd 1 0 >>>> ref TABLE 0x00809800 1 1 >>>> ref N 0x00000080 1 0 >>>> ref CODE 0x00809c00 1 1 >>>> ref _STOP 0x00000001 1 0 >>>> ref _START 0x00000002 1 0 >>>> ref MSG_BOX 0x00809c00 1 1 >>>> ref A_REG 0x00809c01 1 1 >>>> ref B_REG 0x00809c02 1 1 >>>> ref C_REG 0x00809c03 1 1 >>>> ref LOAD 0x00809c04 1 1 >>>> ref WNOISELVL 0x00809c06 2 1 >>>> ref WNOISESCL 0x00809c07 1 1 >>>> ref OFF_LVL 0x00809c08 2 1 >>>> ref MAXTBL 0x00000010 1 0 >>>> ref PHASEx 0x00809c09 1 1 >>>> ref FTBL 0x00809c3a 1 1 >>>> ref First_Add 0x00809c3b 1 1 >>>> ref Last_Add 0x00809c3c 1 1 >>>> ref FLAGS 0x00809c3d 1 1 >>>> ref NF 0x00809c3e 2 1 >>>> ref S0_gctrl_val 0x00809c3f 1 1 >>>> ref S0_xctrl_val 0x00809c40 1 1 >>>> ref S0_rctrl_val 0x00809c41 1 1 >>>> ref PHASE 0x00000000 1 0 >>>> ref OFFS 0x00000001 1 0 >>>> ref A_LVL 0x00000002 1 0 >>>> ref main 0x00809c42 1 1 >>>> ref INITBL 0x00809c4d 1 1 >>>> ref MinS 0x00809c51 2 1 >>>> ref MaxS 0x00809c52 2 1 >>>> ref RACC 0x00000000 1 0 >>>> ref IACC 0x00000001 1 0 >>>> ref RSIG 0x00000002 1 0 >>>> ref ISIG 0x00000003 1 0 >>>> ref MAGN 0x00000004 1 0 >>>> ref pi 0x40490fdb 2 0 >>>> ref Rpi 0x3c8efa35 2 0 >>>> ref SFFTdata 0x00809c53 1 1 >>>> ref FX 0x00809c5f 2 1 >>>> ref ADC 0x00809c60 1 1 >>>> ref DAC 0x00809c69 1 1 >>>> ref NextPair 0x00809c79 1 1 >>>> ref Bypass 0x00809c7e 1 1 >>>> ref ADD_NOISE 0x00809c95 1 1 >>>> ref NO_NOISE 0x00809c9a 1 1 >>>> ref RANDX 0x00809cad 1 1 >>>> ref RAND 0x00809cae 1 1 >>>> ref A 0x00809cb2 1 1 >>>> ref C 0x00809cb3 1 1 >>>> ref SEED 0x00809cb4 1 1 >>>> ref SATURATE 0x00809cb5 1 1 >>>> ref UNSATUR8 0x00809cb6 1 1 >>>> ref GIE 0x00002000 1 0 >>>> ref myidle 0x00809cb7 1 1 >>>> ref prog_AIC 0x00809cbc 1 1 >>>> ref AIC_INIT 0x00809cce 1 1 >>>> ref AIC_reset 0x00809cd1 1 1 >>>> ref ST_STUB 0x00809ce9 1 1 >>>> ref stack 0x00809d02 1 1 >>>> ref SP0VECTS 0x00809fc5 1 1 >>>> >>>> Output section start end length >>>> sect Default_sect 0x00809802 0x00809802 0x00000000 >>>> sect TABLE 0x00809800 0x00809800 0x00000000 >>>> sect CODE 0x00809c00 0x00809d03 0x00000103 >>>> sect SP0VECTS 0x00809fc5 0x00809fc7 0x00000002 >>>> >>>> >>>> END DSK