Time-Domain Equalization for ADSL Transceivers

Prof. Brian L. Evans
Department of Electrical and Computer Engineering
The University of Texas at Austin

Friday, February 2nd, 3:00 PM, ENS 302

bevans@ece.utexas.edu

Key Graduate Students: Guner Arslan, Ming Ding, Biao Lu, and Milos Milosevic

Key Undergraduate Students: Jerel Canales, David Love, Scott Margo, and Jeff Wu

Other Key Collaborators: Lloyd Clark and Sayfe Kiaei

Talk - ADSL Information

Abstract

G.DMT and G.lite Asymmetric Digital Subscriber Line (ADSL) modems rely on discrete multitone modulation (DMT). DMT divides a broadband channel into many narrowband subchannels and modulates encoded signals onto the narrowband subchannels by using the fast Fourier transform (FFT). An ADSL receiver employs a finite impulse response filter to shorten the effective duration of the channel impulse response. At the TEQ output, the linear convolution of the transmitted signal and the equalized channel can be viewed as circular convolution. The frequency response of the equalized channel can be compensated by multiplying each FFT coefficient after demodulation with the inverse of the channel response for that frequency bin.

The talk presents four new methods for time-domain equalizer design we have developed at UT Austin:

  1. two suboptimal divide-and-conquer greedy algorithms
  2. a Maximum Channel Capacity method to maximize bit rate
  3. a Minimum Intersymbol Interference (Min-ISI) method that reaches 99% of the maximum bit rate
The Min-ISI method generalizes the Maximum Shortening SNR (MSSNR) method by weighting the ISI in the frequency domain. One surprising result is that the Min-ISI method can reduce the number of TEQ taps by a factor of ten over the classic Minimum Mean Squared Error method and yet achieve the same bit rate in simulation of a digitized ADSL system.

The Min-ISI method and the two greedy algorithms are suitable for real-time implementation on fixed-point digital signal processors. We have implemented the Min-ISI method (and hence the MSSNR method) in real time on the TI TMS320C6200 and TMS320C54 fixed-point digital signal processors. We have released the TMS320C6200 version at

http://www.ece.utexas.edu/~djlove/464.html

Biography

Brian L. Evans is an Associate Professor in the Department of Electrical and Computer Engineering at The University of Texas at Austin, and the Director of the Embedded Signal Processing Laboratory. His current research focuses on the design and real-time implementation of ADSL/VDSL transceivers, desktop printer pipelines, video codecs, and 3-D sonar imaging systems. His B.S.E.E.C.S. (1987) degree is from the Rose-Hulman Institute of Technology, and his M.S.E.E. (1988) and Ph.D.E.E. (1993) degrees are from the Georgia Institute of Technology. He was a post-doctoral researcher from 1993 to 1996 at UC Berkeley in system-level electronic design automation as part of the Ptolemy project.

A list of Telecommunications and Signal Processing Seminars is available at from the ECE department Web pages under "Seminars". The Web address for the Telecommunications and Signal Processing Seminars is http://signal.ece.utexas.edu/seminars